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Commit b92c6287 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
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drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu 



Some HW ip blocks need call SMU to enter/leave power gate state.
So export common set_powergating_by_smu interface.

1. keep consistent with set_clockgating_by_smu
2. scales easily to powergate other ip(gfx) if necessary

Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3eb6e479

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h

+4 −10
Original line number Diff line number Diff line
@@ -287,12 +287,6 @@ enum amdgpu_pcie_gen { 
#define amdgpu_dpm_force_performance_level(adev, l) \

		((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))



#define amdgpu_dpm_powergate_uvd(adev, g) \

		((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))



#define amdgpu_dpm_powergate_vce(adev, g) \

		((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))



#define amdgpu_dpm_get_current_power_state(adev) \

		((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
@@ -347,6 +341,10 @@ enum amdgpu_pcie_gen { 
		((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\

			(adev)->powerplay.pp_handle, msg_id))



#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \

		((adev)->powerplay.pp_funcs->set_powergating_by_smu(\

			(adev)->powerplay.pp_handle, block_type, gate))



#define amdgpu_dpm_get_power_profile_mode(adev, buf) \

		((adev)->powerplay.pp_funcs->get_power_profile_mode(\

			(adev)->powerplay.pp_handle, buf))
@@ -359,10 +357,6 @@ enum amdgpu_pcie_gen { 
		((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\

			(adev)->powerplay.pp_handle, type, parameter, size))



#define amdgpu_dpm_powergate_mmhub(adev) \

		((adev)->powerplay.pp_funcs->powergate_mmhub( \

		(adev)->powerplay.pp_handle))



struct amdgpu_dpm {

	struct amdgpu_ps        *ps;

	/* number of valid power states */

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+4 −4
Original line number Diff line number Diff line
@@ -1729,10 +1729,10 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) 


void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)

{

	if (adev->powerplay.pp_funcs->powergate_uvd) {

	if (adev->powerplay.pp_funcs->set_powergating_by_smu) {

		/* enable/disable UVD */

		mutex_lock(&adev->pm.mutex);

		amdgpu_dpm_powergate_uvd(adev, !enable);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);

		mutex_unlock(&adev->pm.mutex);

	} else {

		if (enable) {
@@ -1751,10 +1751,10 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) 


void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)

{

	if (adev->powerplay.pp_funcs->powergate_vce) {

	if (adev->powerplay.pp_funcs->set_powergating_by_smu) {

		/* enable/disable VCE */

		mutex_lock(&adev->pm.mutex);

		amdgpu_dpm_powergate_vce(adev, !enable);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);

		mutex_unlock(&adev->pm.mutex);

	} else {

		if (enable) {

drivers/gpu/drm/amd/amdgpu/ci_dpm.c

+14 −1
Original line number Diff line number Diff line
@@ -6767,6 +6767,19 @@ static int ci_dpm_read_sensor(void *handle, int idx, 
	}

}



static int ci_set_powergating_by_smu(void *handle,

				uint32_t block_type, bool gate)

{

	switch (block_type) {

	case AMD_IP_BLOCK_TYPE_UVD:

		ci_dpm_powergate_uvd(handle, gate);

		break;

	default:

		break;

	}

	return 0;

}



static const struct amd_ip_funcs ci_dpm_ip_funcs = {

	.name = "ci_dpm",

	.early_init = ci_dpm_early_init,
@@ -6804,7 +6817,7 @@ static const struct amd_pm_funcs ci_dpm_funcs = { 
	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,

	.force_performance_level = &ci_dpm_force_performance_level,

	.vblank_too_short = &ci_dpm_vblank_too_short,

	.powergate_uvd = &ci_dpm_powergate_uvd,

	.set_powergating_by_smu = &ci_set_powergating_by_smu,

	.set_fan_control_mode = &ci_dpm_set_fan_control_mode,

	.get_fan_control_mode = &ci_dpm_get_fan_control_mode,

	.set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,

drivers/gpu/drm/amd/amdgpu/kv_dpm.c

+14 −1
Original line number Diff line number Diff line
@@ -3306,6 +3306,19 @@ static int kv_dpm_read_sensor(void *handle, int idx, 
	}

}



static int kv_set_powergating_by_smu(void *handle,

				uint32_t block_type, bool gate)

{

	switch (block_type) {

	case AMD_IP_BLOCK_TYPE_UVD:

		kv_dpm_powergate_uvd(handle, gate);

		break;

	default:

		break;

	}

	return 0;

}



static const struct amd_ip_funcs kv_dpm_ip_funcs = {

	.name = "kv_dpm",

	.early_init = kv_dpm_early_init,
@@ -3342,7 +3355,7 @@ static const struct amd_pm_funcs kv_dpm_funcs = { 
	.print_power_state = &kv_dpm_print_power_state,

	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,

	.force_performance_level = &kv_dpm_force_performance_level,

	.powergate_uvd = &kv_dpm_powergate_uvd,

	.set_powergating_by_smu = kv_set_powergating_by_smu,

	.enable_bapm = &kv_dpm_enable_bapm,

	.get_vce_clock_state = amdgpu_get_vce_clock_state,

	.check_state_equal = kv_check_state_equal,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+2 −2
Original line number Diff line number Diff line
@@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, 
						RENG_EXECUTE_ON_REG_UPDATE, 1);

		WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);



		if (adev->powerplay.pp_funcs->powergate_mmhub)

			amdgpu_dpm_powergate_mmhub(adev);

		if (adev->powerplay.pp_funcs->set_powergating_by_smu)

			amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);



	} else {

		pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,