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Commit b92b8b35 authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Ingo Molnar
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locking/arch: Rename set_mb() to smp_store_mb() 



Since set_mb() is really about an smp_mb() -- not a IO/DMA barrier
like mb() rename it to match the recent smp_load_acquire() and
smp_store_release().

Suggested-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent ab3f02fc

Documentation/memory-barriers.txt

+3 −3
Original line number Diff line number Diff line
@@ -1662,7 +1662,7 @@ CPU from reordering them. 


There are some more advanced barrier functions:



 (*) set_mb(var, value)

 (*) smp_store_mb(var, value)



     This assigns the value to the variable and then inserts a full memory

     barrier after it, depending on the function.  It isn't guaranteed to
@@ -1975,7 +1975,7 @@ after it has altered the task state: 
	CPU 1

	===============================

	set_current_state();

	  set_mb();

	  smp_store_mb();

	    STORE current->state

	    <general barrier>

	LOAD event_indicated
@@ -2016,7 +2016,7 @@ between the STORE to indicate the event and the STORE to set TASK_RUNNING: 
	CPU 1				CPU 2

	===============================	===============================

	set_current_state();		STORE event_indicated

	  set_mb();			wake_up();

	  smp_store_mb();		wake_up();

	    STORE current->state	  <write barrier>

	    <general barrier>		  STORE current->state

	LOAD event_indicated

arch/arm/include/asm/barrier.h

+1 −1
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ do { \ 
#define read_barrier_depends()		do { } while(0)

#define smp_read_barrier_depends()	do { } while(0)



#define set_mb(var, value)	do { WRITE_ONCE(var, value); smp_mb(); } while (0)

#define smp_store_mb(var, value)	do { WRITE_ONCE(var, value); smp_mb(); } while (0)



#define smp_mb__before_atomic()	smp_mb()

#define smp_mb__after_atomic()	smp_mb()

arch/arm64/include/asm/barrier.h

+1 −1
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ do { \ 
#define read_barrier_depends()		do { } while(0)

#define smp_read_barrier_depends()	do { } while(0)



#define set_mb(var, value)	do { WRITE_ONCE(var, value); smp_mb(); } while (0)

#define smp_store_mb(var, value)	do { WRITE_ONCE(var, value); smp_mb(); } while (0)

#define nop()		asm volatile("nop");



#define smp_mb__before_atomic()	smp_mb()

arch/ia64/include/asm/barrier.h

+1 −6
Original line number Diff line number Diff line
@@ -77,12 +77,7 @@ do { \ 
	___p1;								\

})



/*

 * XXX check on this ---I suspect what Linus really wants here is

 * acquire vs release semantics but we can't discuss this stuff with

 * Linus just yet.  Grrr...

 */

#define set_mb(var, value)	do { WRITE_ONCE(var, value); mb(); } while (0)

#define smp_store_mb(var, value)	do { WRITE_ONCE(var, value); mb(); } while (0)



/*

 * The group barrier in front of the rsm & ssm are necessary to ensure

arch/metag/include/asm/barrier.h

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ static inline void fence(void) 
#define read_barrier_depends()		do { } while (0)

#define smp_read_barrier_depends()	do { } while (0)



#define set_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)

#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)



#define smp_store_release(p, v)						\

do {									\