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Commit b89359bd authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu into drm-next 

This adds very rudimentary TCON (timing controller for raw LCD displays)
support to enable the bypass mode in order to use the DCU controller on
Freescale/NXP Vybrid SoC's.

Additionally the register clock and pixel clock has been separated, but
are currently still enabled and disabled pairwise.

Other than that, fixes and cleanups accross the driver.

* 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu:
  drm/fsl-dcu: increment version and date
  drm/fsl-dcu: implement lastclose callback
  drm/fsl-dcu: disable output polling on driver unload
  drm/fsl-dcu: deallocate fbdev CMA on unload
  drm/fsl-dcu: use variable name dev for struct drm_device
  drm/fsl-dcu: handle missing panel gracefully
  drm/fsl-dcu: detach panel on destroy
  drm/layerscape: reduce excessive stack usage
  drm/fsl-dcu: add TCON driver
  drm/fsl-dcu: use common clock framework for pixel clock divider
  drm/fsl-dcu: add extra clock for pixel clock
  drm/fsl-dcu: disable clock on initialization failure and remove
parents d3a8f678 0449eefe

Documentation/devicetree/bindings/display/fsl,dcu.txt

+11 −4
Original line number Diff line number Diff line
@@ -6,17 +6,24 @@ Required properties: 
	* "fsl,vf610-dcu".



- reg:			Address and length of the register set for dcu.

- clocks:		From common clock binding: handle to dcu clock.

- clock-names:		From common clock binding: Shall be "dcu".

- clocks:		Handle to "dcu" and "pix" clock (in the order below)

			This can be the same clock (e.g. LS1021a)

			See ../clocks/clock-bindings.txt for details.

- clock-names:		Should be "dcu" and "pix"

			See ../clocks/clock-bindings.txt for details.

- big-endian		Boolean property, LS1021A DCU registers are big-endian.

- fsl,panel:		The phandle to panel node.



Optional properties:

- fsl,tcon:		The phandle to the timing controller node.



Examples:

dcu: dcu@2ce0000 {

	compatible = "fsl,ls1021a-dcu";

	reg = <0x0 0x2ce0000 0x0 0x10000>;

	clocks = <&platform_clk 0>;

	clock-names = "dcu";

	clocks = <&platform_clk 0>, <&platform_clk 0>;

	clock-names = "dcu", "pix";

	big-endian;

	fsl,panel = <&panel>;

	fsl,tcon = <&tcon>;

};

Documentation/devicetree/bindings/display/fsl,tcon.txt

0 → 100644
+18 −0
Original line number Diff line number Diff line 
Device Tree bindings for Freescale TCON Driver



Required properties:

- compatible:		Should be one of

	* "fsl,vf610-tcon".



- reg:			Address and length of the register set for tcon.

- clocks:		From common clock binding: handle to tcon ipg clock.

- clock-names:		From common clock binding: Shall be "ipg".



Examples:

timing-controller@4003d000 {

	compatible = "fsl,vf610-tcon";

	reg = <0x4003d000 0x1000>;

	clocks = <&clks VF610_CLK_TCON0>;

	clock-names = "ipg";

	status = "okay";

};

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -3835,6 +3835,7 @@ L: dri-devel@lists.freedesktop.org 
S:	Supported

F:	drivers/gpu/drm/fsl-dcu/

F:	Documentation/devicetree/bindings/display/fsl,dcu.txt

F:	Documentation/devicetree/bindings/display/fsl,tcon.txt

F:	Documentation/devicetree/bindings/display/panel/nec,nl4827hc19_05b.txt



DRM DRIVERS FOR FREESCALE IMX

drivers/gpu/drm/fsl-dcu/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -3,5 +3,6 @@ fsl-dcu-drm-y := fsl_dcu_drm_drv.o \ 
		 fsl_dcu_drm_rgb.o \

		 fsl_dcu_drm_plane.o \

		 fsl_dcu_drm_crtc.o \

		 fsl_dcu_drm_fbdev.o

		 fsl_dcu_drm_fbdev.o \

		 fsl_tcon.o

obj-$(CONFIG_DRM_FSL_DCU)	+= fsl-dcu-drm.o

drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c

+2 −5
Original line number Diff line number Diff line
@@ -67,12 +67,10 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 
	struct drm_device *dev = crtc->dev;

	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;

	struct drm_display_mode *mode = &crtc->state->mode;

	unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index, pol = 0;

	unsigned long dcuclk;

	unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0;



	index = drm_crtc_index(crtc);

	dcuclk = clk_get_rate(fsl_dev->clk);

	div = dcuclk / mode->clock / 1000;

	clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000);



	/* Configure timings: */

	hbp = mode->htotal - mode->hsync_end;
@@ -99,7 +97,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 
	regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,

		     DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |

		     DCU_DISP_SIZE_DELTA_X(mode->hdisplay));

	regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div);

	regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);

	regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |

		     DCU_BGND_G(0) | DCU_BGND_B(0));