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Commit b85ac980 authored by Manaf Meethalavalappu Pallikunhi's avatar Manaf Meethalavalappu Pallikunhi
Browse files

ARM: dts: qcom: Add LMH-DCVSh configuration for BENGAL 

Add LMH-DCVSh hardware configuration like debug interrupt, cluster
affinity value, CPU to LMH-DCVSh hardware mapping etc. for BENGAL.

Change-Id: I78c7bbacb4360c4c6073bbe4190df2843598ac78
parent 2be76c45

qcom/bengal-thermal.dtsi

+24 −0
Original line number Diff line number Diff line 
#include <dt-bindings/thermal/thermal.h>

#include <dt-bindings/thermal/qmi_thermal.h>



&cpufreq_hw {

	#address-cells = <1>;

	#size-cells = <1>;

	lmh_dcvs0: qcom,limits-dcvs@f521000 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;

		reg = <0xf550800 0x1000>,

			<0xf521000 0x1000>;

		qcom,no-cooling-device-register;

		#thermal-sensor-cells = <0>;

	};



	lmh_dcvs1: qcom,limits-dcvs@f523000 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0xf550800 0x1000>,

			<0xf523000 0x1000>;

		qcom,no-cooling-device-register;

		#thermal-sensor-cells = <0>;

	};

};



&soc {

	qmi-tmd-devices {

		compatible = "qcom,qmi-cooling-devices";

qcom/bengal.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_0: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <2>;
@@ -69,6 +70,7 @@ 
			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;



			L1_I_1: l1-icache {

				compatible = "arm,arch-cache";
@@ -90,6 +92,7 @@ 
			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;



			L1_I_2: l1-icache {

				compatible = "arm,arch-cache";
@@ -111,6 +114,7 @@ 
			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;



			L1_I_3: l1-icache {

				compatible = "arm,arch-cache";
@@ -132,6 +136,7 @@ 
			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L2_1: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <2>;
@@ -157,6 +162,7 @@ 
			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;



			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";
@@ -178,6 +184,7 @@ 
			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;



			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";
@@ -199,6 +206,7 @@ 
			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;



			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";