Commit b7dfee24 authored Jun 03, 2017 by Marek Vasut Committed by Philipp Zabel Jun 06, 2017

gpu: ipu-v3: Fix CSI selection for VDIC



The description of the CSI_SEL bit in the i.MX6 reference manual is
incorrect. It states "This bit defines which CSI is the input to the
IC. This bit is effective only if IC_INPUT is bit cleared".

From experiment it was found this is in fact not correct. The CSI_SEL
bit selects which CSI is input to _both_ the VDIC _and_ the IC. If the
IC_INPUT bit is set so that the IC is receiving from the VDIC, the IC
ignores the CSI_SEL bit, but CSI_SEL still selects which CSI the VDIC
receives from in that case.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

parent e36aecba

drivers/gpu/ipu-v3/ipu-common.c

+8 −7

Original line number	Diff line number	Diff line
		@@ -725,15 +725,16 @@ void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
		spin_lock_irqsave(&ipu->lock, flags);

		val = ipu_cm_read(ipu, IPU_CONF);
		if (vdi) {
		if (vdi)
		val \|= IPU_CONF_IC_INPUT;
		} else {
		else
		val &= ~IPU_CONF_IC_INPUT;

		if (csi_id == 1)
		val \|= IPU_CONF_CSI_SEL;
		else
		val &= ~IPU_CONF_CSI_SEL;
		}

		ipu_cm_write(ipu, val, IPU_CONF);

		spin_unlock_irqrestore(&ipu->lock, flags);