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Commit b799207e authored by Jann Horn's avatar Jann Horn Committed by Daniel Borkmann
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bpf: 32-bit RSH verification must truncate input before the ALU op 



When I wrote commit 468f6eaf ("bpf: fix 32-bit ALU op verification"), I
assumed that, in order to emulate 64-bit arithmetic with 32-bit logic, it
is sufficient to just truncate the output to 32 bits; and so I just moved
the register size coercion that used to be at the start of the function to
the end of the function.

That assumption is true for almost every op, but not for 32-bit right
shifts, because those can propagate information towards the least
significant bit. Fix it by always truncating inputs for 32-bit ops to 32
bits.

Also get rid of the coerce_reg_to_size() after the ALU op, since that has
no effect.

Fixes: 468f6eaf ("bpf: fix 32-bit ALU op verification")
Acked-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
Signed-off-by: default avatarJann Horn <jannh@google.com>
Signed-off-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
parent b0584ea6

kernel/bpf/verifier.c

+9 −1
Original line number Original line Diff line number Diff line
@@ -2896,6 +2896,15 @@ static int adjust_scalar_min_max_vals(struct bpf_verifier_env *env, 
	u64 umin_val, umax_val;

	u64 umin_val, umax_val;

	u64 insn_bitness = (BPF_CLASS(insn->code) == BPF_ALU64) ? 64 : 32;

	u64 insn_bitness = (BPF_CLASS(insn->code) == BPF_ALU64) ? 64 : 32;





	if (insn_bitness == 32) {

		/* Relevant for 32-bit RSH: Information can propagate towards

		 * LSB, so it isn't sufficient to only truncate the output to

		 * 32 bits.

		 */

		coerce_reg_to_size(dst_reg, 4);

		coerce_reg_to_size(&src_reg, 4);

	}



	smin_val = src_reg.smin_value;

	smin_val = src_reg.smin_value;

	smax_val = src_reg.smax_value;

	smax_val = src_reg.smax_value;

	umin_val = src_reg.umin_value;

	umin_val = src_reg.umin_value;
@@ -3131,7 +3140,6 @@ static int adjust_scalar_min_max_vals(struct bpf_verifier_env *env, 
	if (BPF_CLASS(insn->code) != BPF_ALU64) {

	if (BPF_CLASS(insn->code) != BPF_ALU64) {

		/* 32-bit ALU ops are (32,32)->32 */

		/* 32-bit ALU ops are (32,32)->32 */

		coerce_reg_to_size(dst_reg, 4);

		coerce_reg_to_size(dst_reg, 4);

		coerce_reg_to_size(&src_reg, 4);

	}

	}





	__reg_deduce_bounds(dst_reg);

	__reg_deduce_bounds(dst_reg);