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Commit b72f81bb authored by Murthy Nidadavolu's avatar Murthy Nidadavolu Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add TSPP node for msm-4.19 kernel 

Add TSPP device tree node to support TSPP on kernel 4.19,
together with the required pinctrl definitions.

Change-Id: I2150224138cc23237c74649429f6fa9577244d3a
parent 013089ef

bindings/platform/msm/msm_demux.txt

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* Demux



Demux is responsible for demuxing the transport stream contents

to respective elementary streams



Required properties:

- compatible : Should be "qcom,demux"



Example:



        demux {

                compatible = "qcom,demux";

        };

bindings/platform/msm/msm_tspp.txt

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* TSPP ( QTI Transport Stream Packet Processor )



Hardware driver for QTI TSIF 12seg wrapper core, which consists of a TSPP, a

BAM (Bus access manager, used for DMA) and two TSIF inputs.



The TSPP driver is responsible for:

 - TSPP/TSIF hardware configuration (using SPS driver to configure BAM hardware)

 - TSIF GPIO/Clocks configuration

 - Memory resource management

 - Handling TSIF/TSPP interrupts and BAM events

 - TSPP Power management



Required properties:

- compatible : Should be "qcom,msm_tspp"

- reg : Specifies the base physical addresses and sizes of TSIF, TSPP & BAM registers.

- reg-names : Specifies the register names of TSIF, TSPP & BAM base registers.

- interrupts : Specifies the interrupts associated with TSIF 12 seg core.

- interrupt-names: Specifies interrupt names for TSIF, TSPP & BAM interrupts.

- clock-names: Specifies the clock names used for interface & reference clocks.

- clocks: GCC_TSIF_AHB_CLK clock for interface clock & GCC_TSIF_REF_CLK clock for reference clock.

- qcom, msm_bus,name: Should be "tsif"

- qcom, msm_bus,num_cases: Depends on the use cases for bus scaling

- qcom, msm_bus,num_paths: The paths for source and destination ports

- qcom, msm_bus,vectors: Vectors for bus topology.

- pinctrl-names: Names for the TSIF mode configuration to specify which TSIF interface is active.

- qcom,smmu-s1-bypass : Boolean flag to bypass SMMU stage 1 translation.

- iommus : A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device.



Example:



        tspp: msm_tspp@0x8880000 {

                compatible = "qcom,msm_tspp";

                reg = <0x088a7000 0x200>, /* MSM_TSIF0_PHYS */

                      <0x088a8000 0x200>, /* MSM_TSIF1_PHYS */

                      <0x088a9000 0x1000>, /* MSM_TSPP_PHYS  */

                      <0x08884000 0x23000>; /* MSM_TSPP_BAM_PHYS */

                reg-names = "MSM_TSIF0_PHYS",

                        "MSM_TSIF1_PHYS",

                        "MSM_TSPP_PHYS",

                        "MSM_TSPP_BAM_PHYS";

                interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */

                        <0 119 0>, /* TSIF0_IRQ */

                        <0 120 0>, /* TSIF1_IRQ */

                        <0 122 0>; /* TSIF_BAM_IRQ */

                interrupt-names = "TSIF_TSPP_IRQ",

                        "TSIF0_IRQ",

                        "TSIF1_IRQ",

                        "TSIF_BAM_IRQ";



                clock-names = "iface_clk", "ref_clk";

                clocks = <&clock_gcc GCC_TSIF_AHB_CLK>,

                        <&clock_gcc GCC_TSIF_REF_CLK>;



                qcom,msm-bus,name = "tsif";

                qcom,msm-bus,num-cases = <2>;

                qcom,msm-bus,num-paths = <1>;

                qcom,msm-bus,vectors-KBps =

                                <82 512 0 0>, /* No vote */

                                <82 512 12288 24576>;

                                /* Max. bandwidth, 2xTSIF, each max of 96Mbps */



                pinctrl-names = "disabled",

                        "tsif0-mode1", "tsif0-mode2",

                        "tsif1-mode1", "tsif1-mode2",

                        "dual-tsif-mode1", "dual-tsif-mode2";



                pinctrl-0 = <>;                         /* disabled */

                pinctrl-1 = <&tsif0_signals_active>;    /* tsif0-mode1 */

                pinctrl-2 = <&tsif0_signals_active

                        &tsif0_sync_active>;            /* tsif0-mode2 */

                pinctrl-3 = <&tsif1_signals_active>;    /* tsif1-mode1 */

                pinctrl-4 = <&tsif1_signals_active

                        &tsif1_sync_active>;            /* tsif1-mode2 */

                pinctrl-5 = <&tsif0_signals_active

                        &tsif1_signals_active>;         /* dual-tsif-mode1 */

                pinctrl-6 = <&tsif0_signals_active

                        &tsif0_sync_active

                        &tsif1_signals_active

                        &tsif1_sync_active>;            /* dual-tsif-mode2 */



                qcom,smmu-s1-bypass;

                iommus = <&apps_smmu 0x20 0x0f>;

    };

qcom/kona-pinctrl.dtsi

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@@ -2660,6 +2660,72 @@ 
			};

		};



		tsif0_signals_active: tsif0_signals_active {

			tsif1_clk {

				pins = "gpio69"; /* TSIF0 CLK */

				function = "tsif0_clk";

			};



			tsif1_en {

				pins = "gpio70"; /* TSIF0 Enable */

				function = "tsif0_en";

			};



			tsif1_data {

				pins = "gpio71"; /* TSIF0 DATA */

				function = "tsif0_data";

			};



			signals_cfg {

				pins = "gpio69", "gpio70", "gpio71";

				drive_strength = <2>;	/* 2 mA */

				bias-pull-down;		/* pull down */

			};

		};



		/* sync signal is only used if configured to mode-2 */

		tsif0_sync_active: tsif0_sync_active {

			tsif1_sync {

				pins = "gpio72";	/* TSIF0 SYNC */

				function = "tsif0_sync";

				drive_strength = <2>;	/* 2 mA */

				bias-pull-down;		/* pull down */

			};

		};



		tsif1_signals_active: tsif1_signals_active {

			tsif2_clk {

				pins = "gpio73"; /* TSIF1 CLK */

				function = "tsif1_clk";

			};



			tsif2_en {

				pins = "gpio74"; /* TSIF1 Enable */

				function = "tsif1_en";

			};



			tsif2_data {

				pins = "gpio75"; /* TSIF1 DATA */

				function = "tsif1_data";

			};



			signals_cfg {

				pins = "gpio73", "gpio74", "gpio75";

				drive_strength = <2>;	/* 2 mA */

				bias-pull-down;		/* pull down */

			};

		};



		/* sync signal is only used if configured to mode-2 */

		tsif1_sync_active: tsif1_sync_active {

			tsif2_sync {

				pins = "gpio76";	/* TSIF1 SYNC */

				function = "tsif1_sync";

				drive_strength = <2>;	/* 2 mA */

				bias-pull-down;		/* pull down */

			};

		};



		bt_en_sleep: bt_en_sleep {

			mux {

			pins = "gpio21";

qcom/kona.dtsi

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@@ -4992,6 +4992,66 @@ 
		qcom,keep-radio-on-during-sleep;

		status = "disabled";

	};



	tspp: msm_tspp@8880000 {

		compatible = "qcom,msm_tspp";

		reg = <0x088a7000 0x200>, /* MSM_TSIF0_PHYS */

		      <0x088a8000 0x200>, /* MSM_TSIF1_PHYS */

		      <0x088a9000 0x1000>, /* MSM_TSPP_PHYS  */

		      <0x08884000 0x23000>; /* MSM_TSPP_BAM_PHYS */

		reg-names = "MSM_TSIF0_PHYS",

			"MSM_TSIF1_PHYS",

			"MSM_TSPP_PHYS",

			"MSM_TSPP_BAM_PHYS";

		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,/*TSIF_TSPP_IRQ*/

			<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, /* TSIF0_IRQ */

			<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, /* TSIF1_IRQ */

			<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; /* TSIF_BAM_IRQ */

		interrupt-names = "TSIF_TSPP_IRQ",

			"TSIF0_IRQ",

			"TSIF1_IRQ",

			"TSIF_BAM_IRQ";



		clock-names = "iface_clk", "ref_clk";

		clocks = <&clock_gcc GCC_TSIF_AHB_CLK>,

			<&clock_gcc GCC_TSIF_REF_CLK>;



		qcom,msm-bus,name = "tsif";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<82 512 0 0>, /* No vote */

				<82 512 12288 24576>;

				/* Max. bandwidth, 2xTSIF, each max of 96Mbps */



		pinctrl-names = "disabled",

			"tsif0-mode1", "tsif0-mode2",

			"tsif1-mode1", "tsif1-mode2",

			"dual-tsif-mode1", "dual-tsif-mode2";



		pinctrl-0 = <>;				/* disabled */

		pinctrl-1 = <&tsif0_signals_active>;	/* tsif0-mode1 */

		pinctrl-2 = <&tsif0_signals_active

			&tsif0_sync_active>;		/* tsif0-mode2 */

		pinctrl-3 = <&tsif1_signals_active>;	/* tsif1-mode1 */

		pinctrl-4 = <&tsif1_signals_active

			&tsif1_sync_active>;		/* tsif1-mode2 */

		pinctrl-5 = <&tsif0_signals_active

			&tsif1_signals_active>;		/* dual-tsif-mode1 */

		pinctrl-6 = <&tsif0_signals_active

			&tsif0_sync_active

			&tsif1_signals_active

			&tsif1_sync_active>;		/* dual-tsif-mode2 */



		memory-region = <&qseecom_mem>;

		iommus = <&apps_smmu 0xA0 0x00>;

		qcom,iommu-dma-addr-pool = <0x10000000  0x40000000>;

		qcom,smmu-s1-enable;

	};



	demux {

		compatible = "qcom,demux";

	};

};



#include "kona-regulators.dtsi"