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Commit b712eb76 authored by Vara Reddy's avatar Vara Reddy
Browse files

drm/msm/dsi-staging: update mdp transfer time preference 



With this change, mdp transfer time updated to userspace
will be the preferred dtsi entry, when both dsi clock
and mdp transfer time nodes are set.

Change-Id: I37cd55e3d6f3f0f78f4ca4bddf921f6cf743c1b9
Signed-off-by: default avatarVara Reddy <varar@codeaurora.org>
parent 9e60a485

msm/dsi/dsi_display.c

+1 −3
Original line number Diff line number Diff line
@@ -5930,9 +5930,7 @@ int dsi_display_get_modes(struct dsi_display *display, 
				display_mode.timing.min_dsi_clk_hz;



			display_mode.priv_info->mdp_transfer_time_us =

				display_mode.priv_info->dsi_transfer_time_us;

			display_mode.timing.mdp_transfer_time_us =

				display_mode.timing.dsi_transfer_time_us;

				display_mode.timing.mdp_transfer_time_us;

		}



		is_split_link = host->split_link.split_link_enabled;

msm/dsi/dsi_panel.c

+8 −0
Original line number Diff line number Diff line
@@ -3646,6 +3646,14 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config, 
			frame_threshold_us;

	}



	timing->mdp_transfer_time_us = timing->dsi_transfer_time_us;



	/* Force update mdp xfer time to hal,if clk and mdp xfer time is set */

	if (mode->priv_info->mdp_transfer_time_us && timing->clk_rate_hz) {

		timing->mdp_transfer_time_us =

			mode->priv_info->mdp_transfer_time_us;

	}



	/* Calculate pclk_khz to update modeinfo */

	pclk_rate_hz = mult_frac(min_bitclk_hz, frame_time_us,

			timing->dsi_transfer_time_us);