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Commit b6f4f1f2 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-samsung-4.8' of git://linuxtv.org/snawrocki/samsung into clk-next 

Merge changes from Sylwester Nawrocki for samsung clk drivers:

 - a fix for exynos7 to prevent gating some critical CMU clocks,
 - addition of CPU clocks for CPU frequency scaling on Exynos5433 SoCs,
 - additions for exynos5410 SoC required for Odroid XU board support,
 - register accessors fixes for kernels built for big endian operation
   (mostly exynos4 SoCs),
 - Exynos5433 clock definitions fixes required for suspend to RAM and
   the audio subsystem operation,
 - many cleanups changing attributes of the clock initializer data

* tag 'clk-samsung-4.8' of git://linuxtv.org/snawrocki/samsung: (41 commits)
  clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device
  clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flags to avoid hang during S2R
  clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD UART
  clk: samsung: exynos4: fixup reg access on be
  clk: samsung: fixup endian in pll clk
  clk: samsung: exynos5410: Add WDT, ACLK266 and SSS clocks
  clk: samsung: exynos5433: add CPU clocks configuration data and instantiate CPU clocks
  clk: samsung: cpu: prepare for adding Exynos5433 CPU clocks
  clk: samsung: exynos5433: prepare for adding CPU clocks
  clk: samsung: Suppress unbinding to prevent theoretical attacks
  clk: samsung: exynos5420: Set ID for aclk333 gate clock
  clk: samsung: exynos5410: Add TMU clock
  clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks
  clk: samsung: exynos5410: Add serial3, USB and PWM clocks
  clk: samsung: exynos3250: Move PLL rates data to init section
  clk: samsung: Fully constify mux parent names
  clk: samsung: exynos5250: Move sleep init function to init section
  clk: samsung: exynos5420: Move sleep init function and PLL data to init section
  clk: samsung: exynos5433: Move PLL rates data to init section
  clk: samsung: exynos5433: Constify all clock initializers
  ...
parents 2d5b520c 0e450447

drivers/clk/samsung/clk-cpu.c

+130 −1
Original line number Diff line number Diff line
@@ -45,6 +45,13 @@ 
#define E4210_DIV_STAT_CPU0	0x400

#define E4210_DIV_STAT_CPU1	0x404



#define E5433_MUX_SEL2		0x008

#define E5433_MUX_STAT2		0x208

#define E5433_DIV_CPU0		0x400

#define E5433_DIV_CPU1		0x404

#define E5433_DIV_STAT_CPU0	0x500

#define E5433_DIV_STAT_CPU1	0x504



#define E4210_DIV0_RATIO0_MASK	0x7

#define E4210_DIV1_HPM_MASK	(0x7 << 4)

#define E4210_DIV1_COPY_MASK	(0x7 << 0)
@@ -252,6 +259,102 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, 
	return 0;

}



/*

 * Helper function to set the 'safe' dividers for the CPU clock. The parameters

 * div and mask contain the divider value and the register bit mask of the

 * dividers to be programmed.

 */

static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,

					unsigned long mask)

{

	unsigned long div0;



	div0 = readl(base + E5433_DIV_CPU0);

	div0 = (div0 & ~mask) | (div & mask);

	writel(div0, base + E5433_DIV_CPU0);

	wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask);

}



/* handler for pre-rate change notification from parent clock */

static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,

			struct exynos_cpuclk *cpuclk, void __iomem *base)

{

	const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;

	unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent);

	unsigned long alt_div = 0, alt_div_mask = DIV_MASK;

	unsigned long div0, div1 = 0, mux_reg;

	unsigned long flags;



	/* find out the divider values to use for clock data */

	while ((cfg_data->prate * 1000) != ndata->new_rate) {

		if (cfg_data->prate == 0)

			return -EINVAL;

		cfg_data++;

	}



	spin_lock_irqsave(cpuclk->lock, flags);



	/*

	 * For the selected PLL clock frequency, get the pre-defined divider

	 * values.

	 */

	div0 = cfg_data->div0;

	div1 = cfg_data->div1;



	/*

	 * If the old parent clock speed is less than the clock speed of

	 * the alternate parent, then it should be ensured that at no point

	 * the armclk speed is more than the old_prate until the dividers are

	 * set.  Also workaround the issue of the dividers being set to lower

	 * values before the parent clock speed is set to new lower speed

	 * (this can result in too high speed of armclk output clocks).

	 */

	if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {

		unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);



		alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;

		WARN_ON(alt_div >= MAX_DIV);



		exynos5433_set_safe_div(base, alt_div, alt_div_mask);

		div0 |= alt_div;

	}



	/* select the alternate parent */

	mux_reg = readl(base + E5433_MUX_SEL2);

	writel(mux_reg | 1, base + E5433_MUX_SEL2);

	wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2);



	/* alternate parent is active now. set the dividers */

	writel(div0, base + E5433_DIV_CPU0);

	wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL);



	writel(div1, base + E5433_DIV_CPU1);

	wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL);



	spin_unlock_irqrestore(cpuclk->lock, flags);

	return 0;

}



/* handler for post-rate change notification from parent clock */

static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,

			struct exynos_cpuclk *cpuclk, void __iomem *base)

{

	unsigned long div = 0, div_mask = DIV_MASK;

	unsigned long mux_reg;

	unsigned long flags;



	spin_lock_irqsave(cpuclk->lock, flags);



	/* select apll as the alternate parent */

	mux_reg = readl(base + E5433_MUX_SEL2);

	writel(mux_reg & ~1, base + E5433_MUX_SEL2);

	wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1);



	exynos5433_set_safe_div(base, div, div_mask);

	spin_unlock_irqrestore(cpuclk->lock, flags);

	return 0;

}



/*

 * This notifier function is called for the pre-rate and post-rate change

 * notifications of the parent clock of cpuclk.
@@ -275,6 +378,29 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb, 
	return notifier_from_errno(err);

}



/*

 * This notifier function is called for the pre-rate and post-rate change

 * notifications of the parent clock of cpuclk.

 */

static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,

				unsigned long event, void *data)

{

	struct clk_notifier_data *ndata = data;

	struct exynos_cpuclk *cpuclk;

	void __iomem *base;

	int err = 0;



	cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);

	base = cpuclk->ctrl_base;



	if (event == PRE_RATE_CHANGE)

		err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base);

	else if (event == POST_RATE_CHANGE)

		err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base);



	return notifier_from_errno(err);

}



/* helper function to register a CPU clock */

int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,

		unsigned int lookup_id, const char *name, const char *parent,
@@ -301,6 +427,9 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, 
	cpuclk->ctrl_base = ctx->reg_base + offset;

	cpuclk->lock = &ctx->lock;

	cpuclk->flags = flags;

	if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)

		cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;

	else

		cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;



	cpuclk->alt_parent = __clk_lookup(alt_parent);

drivers/clk/samsung/clk-cpu.h

+3 −1
Original line number Diff line number Diff line
@@ -57,10 +57,12 @@ struct exynos_cpuclk { 
	struct notifier_block			clk_nb;

	unsigned long				flags;



/* The CPU clock registers has DIV1 configuration register */

/* The CPU clock registers have DIV1 configuration register */

#define CLK_CPU_HAS_DIV1		(1 << 0)

/* When ALT parent is active, debug clocks need safe divider values */

#define CLK_CPU_NEEDS_DEBUG_ALT_DIV	(1 << 1)

/* The CPU clock registers have Exynos5433-compatible layout */

#define CLK_CPU_HAS_E5433_REGS_LAYOUT	(1 << 2)

};



extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,

drivers/clk/samsung/clk-exynos-clkout.c

+2 −0
Original line number Diff line number Diff line
@@ -151,6 +151,8 @@ static void __init exynos5_clkout_init(struct device_node *node) 
}

CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu",

		exynos5_clkout_init);

CLK_OF_DECLARE(exynos5410_clkout, "samsung,exynos5410-pmu",

		exynos5_clkout_init);

CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu",

		exynos5_clkout_init);

CLK_OF_DECLARE(exynos5433_clkout, "samsung,exynos5433-pmu",

drivers/clk/samsung/clk-exynos3250.c

+21 −20
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ 
#define PWR_CTRL1_USE_CORE1_WFI			(1 << 1)

#define PWR_CTRL1_USE_CORE0_WFI			(1 << 0)



static unsigned long exynos3250_cmu_clk_regs[] __initdata = {

static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {

	SRC_LEFTBUS,

	DIV_LEFTBUS,

	GATE_IP_LEFTBUS,
@@ -226,7 +226,7 @@ PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti", 
PNAME(mout_mfc_p)		= { "mout_mfc_0", "mout_mfc_1" };

PNAME(mout_g3d_p)		= { "mout_g3d_0", "mout_g3d_1" };



static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {

static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {

	FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),

	FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),

	FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
@@ -237,7 +237,7 @@ static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = { 
	FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),

};



static struct samsung_mux_clock mux_clks[] __initdata = {

static const struct samsung_mux_clock mux_clks[] __initconst = {

	/*

	 * NOTE: Following table is sorted by register address in ascending

	 * order and then bitfield shift in descending order, as it is done
@@ -326,7 +326,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { 
			CLK_SET_RATE_PARENT, 0),

};



static struct samsung_div_clock div_clks[] __initdata = {

static const struct samsung_div_clock div_clks[] __initconst = {

	/*

	 * NOTE: Following table is sorted by register address in ascending

	 * order and then bitfield shift in descending order, as it is done
@@ -429,7 +429,7 @@ static struct samsung_div_clock div_clks[] __initdata = { 
	DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),

};



static struct samsung_gate_clock gate_clks[] __initdata = {

static const struct samsung_gate_clock gate_clks[] __initconst = {

	/*

	 * NOTE: Following table is sorted by register address in ascending

	 * order and then bitfield shift in descending order, as it is done
@@ -669,7 +669,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { 
};



/* APLL & MPLL & BPLL & UPLL */

static struct samsung_pll_rate_table exynos3250_pll_rates[] = {

static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {

	PLL_35XX_RATE(1200000000, 400, 4, 1),

	PLL_35XX_RATE(1100000000, 275, 3, 1),

	PLL_35XX_RATE(1066000000, 533, 6, 1),
@@ -691,7 +691,7 @@ static struct samsung_pll_rate_table exynos3250_pll_rates[] = { 
};



/* EPLL */

static struct samsung_pll_rate_table exynos3250_epll_rates[] = {

static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {

	PLL_36XX_RATE(800000000, 200, 3, 1,     0),

	PLL_36XX_RATE(288000000,  96, 2, 2,     0),

	PLL_36XX_RATE(192000000, 128, 2, 3,     0),
@@ -710,7 +710,7 @@ static struct samsung_pll_rate_table exynos3250_epll_rates[] = { 
};



/* VPLL */

static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {

static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {

	PLL_36XX_RATE(600000000, 100, 2, 1,     0),

	PLL_36XX_RATE(533000000, 266, 3, 2, 32768),

	PLL_36XX_RATE(519230987, 173, 2, 2,  5046),
@@ -740,7 +740,7 @@ static struct samsung_pll_rate_table exynos3250_vpll_rates[] = { 
	{ /* sentinel */ }

};



static struct samsung_pll_clock exynos3250_plls[] __initdata = {

static const struct samsung_pll_clock exynos3250_plls[] __initconst = {

	PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",

		APLL_LOCK, APLL_CON0, exynos3250_pll_rates),

	PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
@@ -772,7 +772,7 @@ static void __init exynos3_core_down_clock(void __iomem *reg_base) 
	__raw_writel(0x0, reg_base + PWR_CTRL2);

}



static struct samsung_cmu_info cmu_info __initdata = {

static const struct samsung_cmu_info cmu_info __initconst = {

	.pll_clks		= exynos3250_plls,

	.nr_pll_clks		= ARRAY_SIZE(exynos3250_plls),

	.mux_clks		= mux_clks,
@@ -848,7 +848,7 @@ CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); 
#define EPLL_CON2		0x111c

#define SRC_EPLL		0x1120



static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = {

static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {

	BPLL_LOCK,

	BPLL_CON0,

	BPLL_CON1,
@@ -874,7 +874,7 @@ PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; 
PNAME(mout_mpll_mif_p)	= { "fin_pll", "sclk_mpll_mif", };

PNAME(mout_dphy_p)	= { "mout_mpll_mif", "mout_bpll", };



static struct samsung_mux_clock dmc_mux_clks[] __initdata = {

static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {

	/*

	 * NOTE: Following table is sorted by register address in ascending

	 * order and then bitfield shift in descending order, as it is done
@@ -893,7 +893,7 @@ static struct samsung_mux_clock dmc_mux_clks[] __initdata = { 
	MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),

};



static struct samsung_div_clock dmc_div_clks[] __initdata = {

static const struct samsung_div_clock dmc_div_clks[] __initconst = {

	/*

	 * NOTE: Following table is sorted by register address in ascending

	 * order and then bitfield shift in descending order, as it is done
@@ -910,14 +910,14 @@ static struct samsung_div_clock dmc_div_clks[] __initdata = { 
	DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),

};



static struct samsung_pll_clock exynos3250_dmc_plls[] __initdata = {

static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {

	PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",

		BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),

	PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",

		EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),

};



static struct samsung_cmu_info dmc_cmu_info __initdata = {

static const struct samsung_cmu_info dmc_cmu_info __initconst = {

	.pll_clks		= exynos3250_dmc_plls,

	.nr_pll_clks		= ARRAY_SIZE(exynos3250_dmc_plls),

	.mux_clks		= dmc_mux_clks,
@@ -947,7 +947,7 @@ CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc", 
#define GATE_IP_ISP1		0x804

#define GATE_SCLK_ISP		0x900



static struct samsung_div_clock isp_div_clks[] __initdata = {

static const struct samsung_div_clock isp_div_clks[] __initconst = {

	/*

	 * NOTE: Following table is sorted by register address in ascending

	 * order and then bitfield shift in descending order, as it is done
@@ -967,7 +967,7 @@ static struct samsung_div_clock isp_div_clks[] __initdata = { 
	DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),

};



static struct samsung_gate_clock isp_gate_clks[] __initdata = {

static const struct samsung_gate_clock isp_gate_clks[] __initconst = {

	/*

	 * NOTE: Following table is sorted by register address in ascending

	 * order and then bitfield shift in descending order, as it is done
@@ -1063,7 +1063,7 @@ static struct samsung_gate_clock isp_gate_clks[] __initdata = { 
		GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),

};



static struct samsung_cmu_info isp_cmu_info __initdata = {

static const struct samsung_cmu_info isp_cmu_info __initconst = {

	.div_clks	= isp_div_clks,

	.nr_div_clks	= ARRAY_SIZE(isp_div_clks),

	.gate_clks	= isp_gate_clks,
@@ -1079,14 +1079,15 @@ static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev) 
	return 0;

}



static const struct of_device_id exynos3250_cmu_isp_of_match[] = {

static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {

	{ .compatible = "samsung,exynos3250-cmu-isp", },

	{ /* sentinel */ }

};



static struct platform_driver exynos3250_cmu_isp_driver = {

static struct platform_driver exynos3250_cmu_isp_driver __initdata = {

	.driver = {

		.name = "exynos3250-cmu-isp",

		.suppress_bind_attrs = true,

		.of_match_table = exynos3250_cmu_isp_of_match,

	},

};

drivers/clk/samsung/clk-exynos4.c

+31 −33
Original line number Diff line number Diff line
@@ -169,7 +169,7 @@ static struct samsung_clk_reg_dump *exynos4_save_pll; 
 * list of controller registers to be saved and restored during a

 * suspend/resume cycle.

 */

static unsigned long exynos4210_clk_save[] __initdata = {

static const unsigned long exynos4210_clk_save[] __initconst = {

	E4210_SRC_IMAGE,

	E4210_SRC_LCD1,

	E4210_SRC_MASK_LCD1,
@@ -181,7 +181,7 @@ static unsigned long exynos4210_clk_save[] __initdata = { 
	PWR_CTRL1,

};



static unsigned long exynos4x12_clk_save[] __initdata = {

static const unsigned long exynos4x12_clk_save[] __initconst = {

	E4X12_GATE_IP_IMAGE,

	E4X12_GATE_IP_PERIR,

	E4X12_SRC_CAM1,
@@ -192,7 +192,7 @@ static unsigned long exynos4x12_clk_save[] __initdata = { 
	E4X12_PWR_CTRL2,

};



static unsigned long exynos4_clk_pll_regs[] __initdata = {

static const unsigned long exynos4_clk_pll_regs[] __initconst = {

	EPLL_LOCK,

	VPLL_LOCK,

	EPLL_CON0,
@@ -203,7 +203,7 @@ static unsigned long exynos4_clk_pll_regs[] __initdata = { 
	VPLL_CON2,

};



static unsigned long exynos4_clk_regs[] __initdata = {

static const unsigned long exynos4_clk_regs[] __initconst = {

	SRC_LEFTBUS,

	DIV_LEFTBUS,

	GATE_IP_LEFTBUS,
@@ -505,28 +505,28 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata 
};



/* fixed rate clocks generated inside the soc */

static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {

static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = {

	FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),

	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),

	FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),

};



static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {

static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = {

	FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),

};



static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = {

static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = {

	FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),

	FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),

	FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),

	FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),

};



static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = {

static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = {

	FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),

};



static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initdata = {

static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = {

	FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),

	FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),

	FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
@@ -534,7 +534,7 @@ static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initda 
};



/* list of mux clocks supported in all exynos4 soc's */

static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {

static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {

	MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,

			CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0,

			"mout_apll"),
@@ -555,11 +555,11 @@ static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 
};



/* list of mux clocks supported in exynos4210 soc */

static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {

static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {

	MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),

};



static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {

static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {

	MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),

	MUX(0, "mout_clkout_leftbus", clkout_left_p4210,

			CLKOUT_CMU_LEFTBUS, 0, 5),
@@ -622,7 +622,7 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 
};



/* list of mux clocks supported in exynos4x12 soc */

static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {

static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = {

	MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),

	MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),

	MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
@@ -705,7 +705,7 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 
};



/* list of divider clocks supported in all exynos4 soc's */

static struct samsung_div_clock exynos4_div_clks[] __initdata = {

static const struct samsung_div_clock exynos4_div_clks[] __initconst = {

	DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),

	DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),

	DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
@@ -795,7 +795,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { 
};



/* list of divider clocks supported in exynos4210 soc */

static struct samsung_div_clock exynos4210_div_clks[] __initdata = {

static const struct samsung_div_clock exynos4210_div_clks[] __initconst = {

	DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),

	DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),

	DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
@@ -806,7 +806,7 @@ static struct samsung_div_clock exynos4210_div_clks[] __initdata = { 
};



/* list of divider clocks supported in exynos4x12 soc */

static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {

static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {

	DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),

	DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),

	DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
@@ -837,7 +837,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { 
};



/* list of gate clocks supported in all exynos4 soc's */

static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {

static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {

	/*

	 * After all Exynos4 based platforms are migrated to use device tree,

	 * the device name and clock alias names specified below for some
@@ -1043,7 +1043,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 
};



/* list of gate clocks supported in exynos4210 soc */

static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {

static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = {

	GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),

	GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),

	GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
@@ -1090,7 +1090,7 @@ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 
};



/* list of gate clocks supported in exynos4x12 soc */

static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {

static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {

	GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),

	GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),

	GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
@@ -1190,17 +1190,17 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 
		0),

};



static struct samsung_clock_alias exynos4_aliases[] __initdata = {

static const struct samsung_clock_alias exynos4_aliases[] __initconst = {

	ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),

	ALIAS(CLK_ARM_CLK, NULL, "armclk"),

	ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),

};



static struct samsung_clock_alias exynos4210_aliases[] __initdata = {

static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {

	ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),

};



static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {

static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {

	ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),

};
@@ -1211,7 +1211,7 @@ static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { 
 * controller is first remapped and the value of XOM[0] bit is read to

 * determine the parent clock.

 */

static unsigned long exynos4_get_xom(void)

static unsigned long __init exynos4_get_xom(void)

{

	unsigned long xom = 0;

	void __iomem *chipid_base;
@@ -1264,7 +1264,7 @@ static const struct of_device_id ext_clk_match[] __initconst = { 
};



/* PLLs PMS values */

static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = {

static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {

	PLL_45XX_RATE(1200000000, 150,  3, 1, 28),

	PLL_45XX_RATE(1000000000, 250,  6, 1, 28),

	PLL_45XX_RATE( 800000000, 200,  6, 1, 28),
@@ -1277,7 +1277,7 @@ static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = { 
	{ /* sentinel */ }

};



static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = {

static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {

	PLL_4600_RATE(192000000, 48, 3, 1,     0, 0),

	PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),

	PLL_4600_RATE(180000000, 45, 3, 1,     0, 0),
@@ -1288,7 +1288,7 @@ static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = { 
	{ /* sentinel */ }

};



static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = {

static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {

	PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0),

	PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1,  1, 1),

	PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),
@@ -1297,7 +1297,7 @@ static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = { 
	{ /* sentinel */ }

};



static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = {

static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {

	PLL_35XX_RATE(1500000000, 250, 4, 0),

	PLL_35XX_RATE(1400000000, 175, 3, 0),

	PLL_35XX_RATE(1300000000, 325, 6, 0),
@@ -1315,7 +1315,7 @@ static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = { 
	{ /* sentinel */ }

};



static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = {

static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {

	PLL_36XX_RATE(192000000, 48, 3, 1,     0),

	PLL_36XX_RATE(180633605, 45, 3, 1, 10381),

	PLL_36XX_RATE(180000000, 45, 3, 1,     0),
@@ -1326,7 +1326,7 @@ static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = { 
	{ /* sentinel */ }

};



static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = {

static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {

	PLL_36XX_RATE(533000000, 133, 3, 1, 16384),

	PLL_36XX_RATE(440000000, 110, 3, 1,     0),

	PLL_36XX_RATE(350000000, 175, 3, 2,     0),
@@ -1375,12 +1375,12 @@ static void __init exynos4x12_core_down_clock(void) 
	if (num_possible_cpus() == 4)

		tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |

		       PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;

	__raw_writel(tmp, reg_base + PWR_CTRL1);

	writel_relaxed(tmp, reg_base + PWR_CTRL1);



	/*

	 * Disable the clock up feature in case it was enabled by bootloader.

	 */

	__raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);

	writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);

}



#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0)	\
@@ -1450,8 +1450,6 @@ static void __init exynos4_clk_init(struct device_node *np, 
		panic("%s: failed to map registers\n", __func__);



	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	if (!ctx)

		panic("%s: unable to allocate context.\n", __func__);



	samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,

			ARRAY_SIZE(exynos4_fixed_rate_ext_clks),