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Commit b69b913a authored by Prakash Kamliya's avatar Prakash Kamliya Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Add support for A620 GPU 



Add new GPU chip id and required code to
support A620 GPU.

Change-Id: I119a65edb53dc96f33d6906c03c39536a51a537b
Signed-off-by: default avatarPrakash Kamliya <pkamliya@codeaurora.org>
parent 6982e158

drivers/gpu/msm/adreno-gpulist.h

+41 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pm4fw_name = "a300_pm4.fw",

		.pfpfw_name = "a300_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.busy_mask = 0x7FFFFFFE,

	},
@@ -29,6 +30,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pm4fw_name = "a300_pm4.fw",

		.pfpfw_name = "a300_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.busy_mask = 0x7FFFFFFE,

	},
@@ -42,6 +44,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pm4fw_name = "a300_pm4.fw",

		.pfpfw_name = "a300_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_base = 0,

		.gmem_size = (SZ_64K + SZ_32K),

		.busy_mask = 0x7FFFFFFE,

	},
@@ -98,6 +101,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a530_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.gpmufw_name = "a530_gpmu.fw2",
@@ -123,6 +127,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a530_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.gpmufw_name = "a530v3_gpmu.fw2",
@@ -145,6 +150,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -161,6 +167,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a506_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -174,6 +181,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_256K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -199,6 +207,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a540_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -220,6 +229,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a512_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_256K + SZ_16K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -236,6 +246,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a508_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -260,6 +271,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a630_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -283,6 +295,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a615_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -304,6 +317,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a615_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -313,6 +327,28 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.prim_fifo_threshold = 0x0018000,

		.pdc_address_offset = 0x00030090,

	},

	{

		.gpurev = ADRENO_REV_A620,

		.core = 6,

		.major = 2,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU,

		.sqefw_name = "a650_sqe.fw",

		.zap_name = "a620_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x30,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a650_gmu.bin",

		.gpmu_major = 0x2,

		.gpmu_minor = 0x000,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.prim_fifo_threshold = 0x100000,

		.pdc_address_offset = 0x000300A0,

	},

	{

		.gpurev = ADRENO_REV_A640,

		.core = 6,
@@ -325,6 +361,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a640_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M, //Verified 1MB

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -347,6 +384,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.sqefw_name = "a650_sqe.fw",

		.zap_name = "a650_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.num_protected_regs = 0x30,

		.busy_mask = 0xFFFFFFFE,
@@ -368,6 +406,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a640_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_2M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -391,6 +430,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a612_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,
@@ -410,6 +450,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a615_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

drivers/gpu/msm/adreno.c

+3 −16
Original line number Diff line number Diff line
@@ -67,7 +67,6 @@ static struct adreno_device device_3d0 = { 
		.shadermemname = "kgsl_3d0_shader_memory",

		.ftbl = &adreno_functable,

	},

	.gmem_size = SZ_256K,

	.ft_policy = KGSL_FT_DEFAULT_POLICY,

	.ft_pf_policy = KGSL_FT_PAGEFAULT_DEFAULT_POLICY,

	.long_ib_detect = 1,
@@ -800,13 +799,6 @@ static int adreno_identify_gpu(struct adreno_device *adreno_dev) 
		return -ENODEV;

	}



	/*

	 * The gmem size might be dynamic when ocmem is involved so copy it out

	 * of the gpu device

	 */



	adreno_dev->gmem_size = adreno_dev->gpucore->gmem_size;



	/*

	 * Initialize uninitialzed gpu registers, only needs to be done once

	 * Make all offsets that are not initialized to ADRENO_REG_UNUSED
@@ -2284,8 +2276,8 @@ static int adreno_prop_device_info(struct kgsl_device *device, 
		.device_id = device->id + 1,

		.chip_id = adreno_dev->chipid,

		.mmu_enabled = MMU_FEATURE(&device->mmu, KGSL_MMU_PAGED),

		.gmem_gpubaseaddr = adreno_dev->gmem_base,

		.gmem_sizebytes = adreno_dev->gmem_size,

		.gmem_gpubaseaddr = adreno_dev->gpucore->gmem_base,

		.gmem_sizebytes = adreno_dev->gpucore->gmem_size,

	};



	return copy_prop(value, count, &devinfo, sizeof(devinfo));
@@ -2358,12 +2350,7 @@ static int adreno_prop_uche_gmem_addr(struct kgsl_device *device, 
		u32 type, void __user *value, size_t count)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	u64 vaddr;



	if (ADRENO_GPUREV(adreno_dev) >= 500 && !(adreno_is_a650(adreno_dev)))

		vaddr = ADRENO_UCHE_GMEM_BASE;

	else

		vaddr = 0;

	u64 vaddr = adreno_dev->gpucore->gmem_base;



	return copy_prop(value, count, &vaddr, sizeof(vaddr));

}

drivers/gpu/msm/adreno.h

+23 −8
Original line number Diff line number Diff line
@@ -174,8 +174,6 @@ 
 */

#define ADRENO_IDLE_TIMEOUT (20 * 1000)



#define ADRENO_UCHE_GMEM_BASE	0x100000



#define ADRENO_FW_PFP 0

#define ADRENO_FW_SQE 0

#define ADRENO_FW_PM4 1
@@ -206,6 +204,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A615 = 615,

	ADRENO_REV_A616 = 616,

	ADRENO_REV_A618 = 618,

	ADRENO_REV_A620 = 620,

	ADRENO_REV_A630 = 630,

	ADRENO_REV_A640 = 640,

	ADRENO_REV_A650 = 650,
@@ -349,6 +348,7 @@ struct adreno_device_private { 
 * @pfpfw_name: Filename for the PFP firmware

 * @zap_name: Filename for the Zap Shader ucode

 * @gpudev: Pointer to the GPU family specific functions for this core

 * @gmem_base: Base address of binning memory (GMEM/OCMEM)

 * @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core

 * @shader_offset: Offset of shader from gpu reg base

 * @shader_size: Shader size
@@ -373,6 +373,7 @@ struct adreno_gpu_core { 
	const char *sqefw_name;

	const char *zap_name;

	struct adreno_gpudev *gpudev;

	unsigned long gmem_base;

	size_t gmem_size;

	unsigned long shader_offset;

	unsigned int shader_size;
@@ -402,8 +403,6 @@ enum gpu_coresight_sources { 
 * @dev: Reference to struct kgsl_device

 * @priv: Holds the private flags specific to the adreno_device

 * @chipid: Chip ID specific to the GPU

 * @gmem_base: Base physical address of GMEM

 * @gmem_size: GMEM size

 * @cx_misc_len: Length of the CX MISC register block

 * @cx_misc_virt: Pointer where the CX MISC block is mapped

 * @rscc_base: Base physical address of the RSCC
@@ -484,8 +483,6 @@ struct adreno_device { 
	struct kgsl_device dev;    /* Must be first field in this struct */

	unsigned long priv;

	unsigned int chipid;

	unsigned long gmem_base;

	unsigned long gmem_size;

	unsigned long cx_dbgc_base;

	unsigned int cx_dbgc_len;

	void __iomem *cx_dbgc_virt;
@@ -1231,6 +1228,7 @@ static inline int adreno_is_a6xx(struct adreno_device *adreno_dev) 


ADRENO_TARGET(a612, ADRENO_REV_A612)

ADRENO_TARGET(a618, ADRENO_REV_A618)

ADRENO_TARGET(a620, ADRENO_REV_A620)

ADRENO_TARGET(a630, ADRENO_REV_A630)

ADRENO_TARGET(a640, ADRENO_REV_A640)

ADRENO_TARGET(a650, ADRENO_REV_A650)
@@ -1248,12 +1246,29 @@ static inline int adreno_is_a615_family(struct adreno_device *adreno_dev) 
			rev == ADRENO_REV_A618);

}



/*

 * Derived GPUs from A640 needs to be added to this list.

 * A640 and A680 belongs to this family.

 */

static inline int adreno_is_a640_family(struct adreno_device *adreno_dev)

{

	unsigned int rev = ADRENO_GPUREV(adreno_dev);



	return (rev == ADRENO_REV_A640 || rev == ADRENO_REV_A650 ||

			rev == ADRENO_REV_A680);

	return (rev == ADRENO_REV_A640 || rev == ADRENO_REV_A680);

}



/*

 * Derived GPUs from A650 needs to be added to this list.

 * A650 is derived from A640 but register specs has been

 * changed hence do not belongs to A640 family. A620,

 * A660, A690 follows the register specs of A650.

 *

 */

static inline int adreno_is_a650_family(struct adreno_device *adreno_dev)

{

	unsigned int rev = ADRENO_GPUREV(adreno_dev);



	return (rev == ADRENO_REV_A650 || rev == ADRENO_REV_A620);

}



static inline int adreno_is_a640v2(struct adreno_device *adreno_dev)

drivers/gpu/msm/adreno_a5xx.c

+3 −3
Original line number Diff line number Diff line
@@ -1892,11 +1892,11 @@ static void a5xx_start(struct adreno_device *adreno_dev) 


	/* Program the GMEM VA range for the UCHE path */

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MIN_LO,

				ADRENO_UCHE_GMEM_BASE);

			adreno_dev->gpucore->gmem_base);

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x0);

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MAX_LO,

				ADRENO_UCHE_GMEM_BASE +

				adreno_dev->gmem_size - 1);

			adreno_dev->gpucore->gmem_base +

			adreno_dev->gpucore->gmem_size - 1);

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x0);



	/*

drivers/gpu/msm/adreno_a6xx.c

+65 −13
Original line number Diff line number Diff line
@@ -63,6 +63,7 @@ static const struct adreno_vbif_platform a6xx_vbif_platforms[] = { 
	{ adreno_is_a650, a650_gbif },

	{ adreno_is_a680, a640_gbif },

	{ adreno_is_a612, a640_gbif },

	{ adreno_is_a620, a650_gbif },

};



struct kgsl_hwcg_reg {
@@ -347,6 +348,57 @@ static const struct kgsl_hwcg_reg a650_hwcg_regs[] = { 
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},

};



static const struct kgsl_hwcg_reg a620_hwcg_regs[] = {

	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},

	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},

	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},

	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},

	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},

	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},

	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},

	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},

	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},

	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},

	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},

	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},

	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},

	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},

	{A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},

	{A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},

	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},

	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A6XX_RBBM_ISDB_CNT, 0x00000182},

	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},

	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},

	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},

	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},

};



static const struct kgsl_hwcg_reg a612_hwcg_regs[] = {

	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
@@ -408,6 +460,7 @@ static const struct { 
	{adreno_is_a650, a650_hwcg_regs, ARRAY_SIZE(a650_hwcg_regs)},

	{adreno_is_a680, a640_hwcg_regs, ARRAY_SIZE(a640_hwcg_regs)},

	{adreno_is_a612, a612_hwcg_regs, ARRAY_SIZE(a612_hwcg_regs)},

	{adreno_is_a620, a620_hwcg_regs, ARRAY_SIZE(a620_hwcg_regs)},

};



static struct a6xx_protected_regs {
@@ -872,18 +925,17 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
	kgsl_regwrite(device, A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);



	/*

	 * Program the GMEM VA range for the UCHE path.

	 * From Kona onwards the GMEM VA address is 0, and

	 * UCHE_GMEM_RANGE registers are no longer used, so we don't

	 * have to program them.

	 * Some A6xx targets no longer use a programmed GMEM base address

	 * so only write the registers if a non zero address is given

	 * in the GPU list

	 */

	if (!adreno_is_a650(adreno_dev)) {

	if (adreno_dev->gpucore->gmem_base) {

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_LO,

					ADRENO_UCHE_GMEM_BASE);

				adreno_dev->gpucore->gmem_base);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x0);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_LO,

					ADRENO_UCHE_GMEM_BASE +

					adreno_dev->gmem_size - 1);

				adreno_dev->gpucore->gmem_base +

				adreno_dev->gpucore->gmem_size - 1);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_HI, 0x0);

	}
@@ -970,7 +1022,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) 


	mal = (mal == 64) ? 1 : 0;



	uavflagprd_inv = (adreno_is_a650(adreno_dev)) ? 2 : 0;

	uavflagprd_inv = (adreno_is_a650_family(adreno_dev)) ? 2 : 0;



	kgsl_regwrite(device, A6XX_RB_NC_MODE_CNTL, (rgb565_predicator << 11)|

				(upper_bit << 10) | (amsbc << 4) | (mal << 3) |
@@ -989,8 +1041,6 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
	/* Set hang detection threshold to 0x3FFFFF * 16 cycles */

	kgsl_regwrite(device, A6XX_RBBM_INTERFACE_HANG_INT_CNTL,

					(1 << 30) | 0x3fffff);

	if (adreno_is_a650(adreno_dev))

		kgsl_regwrite(device, A6XX_RBBM_NC_MODE_CNTL, 1);



	kgsl_regwrite(device, A6XX_UCHE_CLIENT_PF, 1);
@@ -1292,7 +1342,7 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev) 
	 * so we can come out of secure mode and CP does not drop

	 * the packet.

	 */

	if (adreno_is_a650(adreno_dev))

	if (adreno_is_a650_family(adreno_dev))

		kgsl_regwrite(device, A6XX_CP_APRIV_CNTL, (1 << 2));



	/* Clear the SQE_HALT to start the CP engine */
@@ -1705,7 +1755,9 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) 
		gpu_cntl1_val = (gpu_cntl1_val << A6XX_GPU_LLC_SCID_NUM_BITS)

			| gpu_scid;



	if (adreno_is_a640_family(adreno_dev) || adreno_is_a612(adreno_dev)) {

	if (adreno_is_a640_family(adreno_dev) ||

			adreno_is_a612(adreno_dev) ||

			adreno_is_a650_family(adreno_dev)) {

		kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1,

			A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);

	} else {