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Commit b66f953c authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
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MIPS: Netlogic: Avoid unnecessary cache flushes 



XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache
flushes.

Signed-off-by: default avatarJayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2729/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 11d48aac

arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h

+2 −3
Original line number Diff line number Diff line
@@ -25,13 +25,12 @@ 
#define cpu_has_llsc		1

#define cpu_has_vtag_icache	0

#define cpu_has_dc_aliases	0

#define cpu_has_ic_fills_f_dc	0

#define cpu_has_ic_fills_f_dc	1

#define cpu_has_dsp		0

#define cpu_has_mipsmt		0

#define cpu_has_userlocal	0

#define cpu_icache_snoops_remote_store	0

#define cpu_icache_snoops_remote_store	1



#define cpu_has_nofpuex		0

#define cpu_has_64bits		1



#define cpu_has_mips32r1	1