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Commit b61a4be5 authored by Roland Vossen's avatar Roland Vossen Committed by Greg Kroah-Hartman
Browse files

staging: brcm80211: further simplified register access macro's 



The SELECT_BUS_READ and SELECT_BUS_WRITE macro's always select
a (sdio) bus operation for fullmac, and a memory operation for
softmac. Thus they can be removed by expanding them in place.

Signed-off-by: default avatarRoland Vossen <rvossen@broadcom.com>
Reviewed-by: default avatarArend van Spriel <arend@broadcom.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 44895185

drivers/staging/brcm80211/brcmfmac/dhd_sdio.c

+14 −88
Original line number Original line Diff line number Diff line
@@ -39,102 +39,30 @@ 
#endif

#endif

#endif

#endif





#if defined(BCMSDIO)

#define SELECT_BUS_WRITE(mmap_op, bus_op) bus_op

#define SELECT_BUS_READ(mmap_op, bus_op) bus_op

#else

#define SELECT_BUS_WRITE(mmap_op, bus_op) mmap_op

#define SELECT_BUS_READ(mmap_op, bus_op) mmap_op

#endif



/* register access macros */

/* register access macros */

#ifndef __BIG_ENDIAN

#ifndef __BIG_ENDIAN

#ifndef __mips__

#ifndef __mips__

#define R_REG(r) (\

#define R_REG(r) \

	SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \

	bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))

	readb((volatile u8*)(r)) : \

	sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \

	readl((volatile u32*)(r)), bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \

)

#else				/* __mips__ */

#else				/* __mips__ */

#define R_REG(r) (\

#define R_REG(r) \

	SELECT_BUS_READ( \

		({ \

			__typeof(*(r)) __osl_v; \

			__asm__ __volatile__("sync"); \

			switch (sizeof(*(r))) { \

			case sizeof(u8): \

				__osl_v = readb((volatile u8*)(r)); \

				break; \

			case sizeof(u16): \

				__osl_v = readw((volatile u16*)(r)); \

				break; \

			case sizeof(u32): \

				__osl_v = \

				readl((volatile u32*)(r)); \

				break; \

			} \

			__asm__ __volatile__("sync"); \

			__osl_v; \

		}), \

	({ \

	({ \

		__typeof(*(r)) __osl_v; \

		__typeof(*(r)) __osl_v; \

		__asm__ __volatile__("sync"); \

		__asm__ __volatile__("sync"); \

		__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \

		__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \

		__asm__ __volatile__("sync"); \

		__asm__ __volatile__("sync"); \

		__osl_v; \

		__osl_v; \

		})) \

	})

)

#endif				/* __mips__ */

#endif				/* __mips__ */





#define W_REG(r, v) do { \

#define W_REG(r, v) do { \

	SELECT_BUS_WRITE( \

		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v)); \

		switch (sizeof(*(r))) { \

		case sizeof(u8): \

			writeb((u8)(v), (volatile u8*)(r)); break; \

		case sizeof(u16): \

			writew((u16)(v), (volatile u16*)(r)); break; \

		case sizeof(u32): \

			writel((u32)(v), (volatile u32*)(r)); break; \

		}, \

		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v))); \

	} while (0)

	} while (0)

#else				/* __BIG_ENDIAN */

#else				/* __BIG_ENDIAN */

#define R_REG(r) (\

#define R_REG(r) \

	SELECT_BUS_READ( \

	bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))

		({ \

			__typeof(*(r)) __osl_v; \

			switch (sizeof(*(r))) { \

			case sizeof(u8): \

				__osl_v = \

				readb((volatile u8*)((r)^3)); \

				break; \

			case sizeof(u16): \

				__osl_v = \

				readw((volatile u16*)((r)^2)); \

				break; \

			case sizeof(u32): \

				__osl_v = readl((volatile u32*)(r)); \

				break; \

			} \

			__osl_v; \

		}), \

		bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \

)

#define W_REG(r, v) do { \

#define W_REG(r, v) do { \

	SELECT_BUS_WRITE( \

		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v); \

		switch (sizeof(*(r))) { \

		case sizeof(u8):	\

			writeb((u8)(v), \

			(volatile u8*)((r)^3)); break; \

		case sizeof(u16):	\

			writew((u16)(v), \

			(volatile u16*)((r)^2)); break; \

		case sizeof(u32):	\

			writel((u32)(v), \

			(volatile u32*)(r)); break; \

		}, \

		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v)); \

	} while (0)

	} while (0)

#endif				/* __BIG_ENDIAN */

#endif				/* __BIG_ENDIAN */
@@ -155,8 +83,6 @@ 
#define SET_REG(r, mask, val) \

#define SET_REG(r, mask, val) \

		W_REG((r), ((R_REG(r) & ~(mask)) | (val)))

		W_REG((r), ((R_REG(r) & ~(mask)) | (val)))









#ifdef DHD_DEBUG

#ifdef DHD_DEBUG





/* ARM trap handling */

/* ARM trap handling */

drivers/staging/brcm80211/brcmsmac/wlc_types.h

+47 −69
Original line number Original line Diff line number Diff line
@@ -48,26 +48,18 @@ do { \ 
#endif

#endif

#endif

#endif





#if defined(BCMSDIO)

#define SELECT_BUS_WRITE(mmap_op, bus_op) bus_op

#define SELECT_BUS_READ(mmap_op, bus_op) bus_op

#else

#define SELECT_BUS_WRITE(mmap_op, bus_op) mmap_op

#define SELECT_BUS_READ(mmap_op, bus_op) mmap_op

#endif



/* register access macros */

/* register access macros */

#ifndef __BIG_ENDIAN

#ifndef __BIG_ENDIAN

#ifndef __mips__

#ifndef __mips__

#define R_REG(r) (\

#define R_REG(r) \

	SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \

	({\

		sizeof(*(r)) == sizeof(u8) ? \

		readb((volatile u8*)(r)) : \

		readb((volatile u8*)(r)) : \

		sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \

		sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \

	readl((volatile u32*)(r)), bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \

		readl((volatile u32*)(r)); \

)

	})

#else				/* __mips__ */

#else				/* __mips__ */

#define R_REG(r) (\

#define R_REG(r) \

	SELECT_BUS_READ( \

	({ \

	({ \

		__typeof(*(r)) __osl_v; \

		__typeof(*(r)) __osl_v; \

		__asm__ __volatile__("sync"); \

		__asm__ __volatile__("sync"); \
@@ -85,19 +77,10 @@ do { \ 
		} \

		} \

		__asm__ __volatile__("sync"); \

		__asm__ __volatile__("sync"); \

		__osl_v; \

		__osl_v; \

		}), \

	})

		({ \

			__typeof(*(r)) __osl_v; \

			__asm__ __volatile__("sync"); \

			__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \

			__asm__ __volatile__("sync"); \

			__osl_v; \

		})) \

)

#endif				/* __mips__ */

#endif				/* __mips__ */





#define W_REG(r, v) do { \

#define W_REG(r, v) do { \

	SELECT_BUS_WRITE( \

		switch (sizeof(*(r))) { \

		switch (sizeof(*(r))) { \

		case sizeof(u8): \

		case sizeof(u8): \

			writeb((u8)(v), (volatile u8*)(r)); break; \

			writeb((u8)(v), (volatile u8*)(r)); break; \
@@ -105,12 +88,10 @@ do { \ 
			writew((u16)(v), (volatile u16*)(r)); break; \

			writew((u16)(v), (volatile u16*)(r)); break; \

		case sizeof(u32): \

		case sizeof(u32): \

			writel((u32)(v), (volatile u32*)(r)); break; \

			writel((u32)(v), (volatile u32*)(r)); break; \

		}, \

		}; \

		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v))); \

	} while (0)

	} while (0)

#else				/* __BIG_ENDIAN */

#else				/* __BIG_ENDIAN */

#define R_REG(r) (\

#define R_REG(r) \

	SELECT_BUS_READ( \

	({ \

	({ \

		__typeof(*(r)) __osl_v; \

		__typeof(*(r)) __osl_v; \

		switch (sizeof(*(r))) { \

		switch (sizeof(*(r))) { \
@@ -127,11 +108,9 @@ do { \ 
			break; \

			break; \

		} \

		} \

		__osl_v; \

		__osl_v; \

		}), \

	})

		bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \



)

#define W_REG(r, v) do { \

#define W_REG(r, v) do { \

	SELECT_BUS_WRITE( \

		switch (sizeof(*(r))) { \

		switch (sizeof(*(r))) { \

		case sizeof(u8):	\

		case sizeof(u8):	\

			writeb((u8)(v), \

			writeb((u8)(v), \
@@ -142,8 +121,7 @@ do { \ 
		case sizeof(u32):	\

		case sizeof(u32):	\

			writel((u32)(v), \

			writel((u32)(v), \

			(volatile u32*)(r)); break; \

			(volatile u32*)(r)); break; \

		}, \

		} \

		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v)); \

	} while (0)

	} while (0)

#endif				/* __BIG_ENDIAN */

#endif				/* __BIG_ENDIAN */