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Commit b60f2f66 authored by Jon Medhurst's avatar Jon Medhurst Committed by Greg Kroah-Hartman
Browse files

serial: amba-pl011: factor out code for writing LCR_H register 



The code to cope with a split tx/rx LCR_H register is non-trivial
so put it into it's own function to avoid duplication.

Signed-off-by: default avatarJon Medhurst <tixy@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent fe433907

drivers/tty/serial/amba-pl011.c

+17 −22
Original line number Diff line number Diff line
@@ -1511,6 +1511,21 @@ static int pl011_hwinit(struct uart_port *port) 
	return retval;

}



static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)

{

	writew(lcr_h, uap->port.membase + uap->lcrh_rx);

	if (uap->lcrh_rx != uap->lcrh_tx) {

		int i;

		/*

		 * Wait 10 PCLKs before writing LCRH_TX register,

		 * to get this delay write read only register 10 times

		 */

		for (i = 0; i < 10; ++i)

			writew(0xff, uap->port.membase + UART011_MIS);

		writew(lcr_h, uap->port.membase + uap->lcrh_tx);

	}

}



static int pl011_startup(struct uart_port *port)

{

	struct uart_amba_port *uap = (struct uart_amba_port *)port;
@@ -1541,17 +1556,7 @@ static int pl011_startup(struct uart_port *port) 
	writew(cr, uap->port.membase + UART011_CR);

	writew(0, uap->port.membase + UART011_FBRD);

	writew(1, uap->port.membase + UART011_IBRD);

	writew(0, uap->port.membase + uap->lcrh_rx);

	if (uap->lcrh_tx != uap->lcrh_rx) {

		int i;

		/*

		 * Wait 10 PCLKs before writing LCRH_TX register,

		 * to get this delay write read only register 10 times

		 */

		for (i = 0; i < 10; ++i)

			writew(0xff, uap->port.membase + UART011_MIS);

		writew(0, uap->port.membase + uap->lcrh_tx);

	}

	pl011_write_lcr_h(uap, 0);

	writew(0, uap->port.membase + UART01x_DR);

	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)

		barrier();
@@ -1801,17 +1806,7 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, 
	 * UART011_FBRD & UART011_IBRD.

	 * ----------^----------^----------^----------^-----

	 */

	writew(lcr_h, port->membase + uap->lcrh_rx);

	if (uap->lcrh_rx != uap->lcrh_tx) {

		int i;

		/*

		 * Wait 10 PCLKs before writing LCRH_TX register,

		 * to get this delay write read only register 10 times

		 */

		for (i = 0; i < 10; ++i)

			writew(0xff, uap->port.membase + UART011_MIS);

		writew(lcr_h, port->membase + uap->lcrh_tx);

	}

	pl011_write_lcr_h(uap, lcr_h);

	writew(old_cr, port->membase + UART011_CR);



	spin_unlock_irqrestore(&port->lock, flags);