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Commit b5954464 authored by Alexander Duyck's avatar Alexander Duyck Committed by David S. Miller
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e1000: allow option to limit number of descriptors down to 48 per ring



This change makes it possible to limit the number of descriptors down to 48
per ring.  The reason for this change is to address a variation on hardware
errata 10 for 82546GB in which descriptors will be lost if more than 32
descriptors are fetched and the PCI-X MRBC is 512.

Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Tested-by: default avatarEmil Tantilov <emil.s.tantilov@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 65395482
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+2 −2
Original line number Original line Diff line number Diff line
@@ -86,12 +86,12 @@ struct e1000_adapter;
/* TX/RX descriptor defines */
/* TX/RX descriptor defines */
#define E1000_DEFAULT_TXD                  256
#define E1000_DEFAULT_TXD                  256
#define E1000_MAX_TXD                      256
#define E1000_MAX_TXD                      256
#define E1000_MIN_TXD                       80
#define E1000_MIN_TXD                       48
#define E1000_MAX_82544_TXD               4096
#define E1000_MAX_82544_TXD               4096


#define E1000_DEFAULT_RXD                  256
#define E1000_DEFAULT_RXD                  256
#define E1000_MAX_RXD                      256
#define E1000_MAX_RXD                      256
#define E1000_MIN_RXD                       80
#define E1000_MIN_RXD                       48
#define E1000_MAX_82544_RXD               4096
#define E1000_MAX_82544_RXD               4096


#define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */
#define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */