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Commit b594272c authored by Bryan Wu's avatar Bryan Wu
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[Blackfin] arch: remove TWI I2C register accessing helper macros, because we... 


[Blackfin] arch: remove TWI I2C register accessing helper macros, because we moved to use i2c new-style interface

Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 904656cd

include/asm-blackfin/mach-bf527/cdefBF52x_base.h

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@@ -873,39 +873,6 @@ 








/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/

/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/

#define bfin_read_TWI_CLKDIV()			bfin_read16(TWI_CLKDIV)

#define bfin_write_TWI_CLKDIV(val)		bfin_write16(TWI_CLKDIV, val)

#define bfin_read_TWI_CONTROL()			bfin_read16(TWI_CONTROL)

#define bfin_write_TWI_CONTROL(val)		bfin_write16(TWI_CONTROL, val)

#define bfin_read_TWI_SLAVE_CTL()		bfin_read16(TWI_SLAVE_CTL)

#define bfin_write_TWI_SLAVE_CTL(val)		bfin_write16(TWI_SLAVE_CTL, val)

#define bfin_read_TWI_SLAVE_STAT()		bfin_read16(TWI_SLAVE_STAT)

#define bfin_write_TWI_SLAVE_STAT(val)		bfin_write16(TWI_SLAVE_STAT, val)

#define bfin_read_TWI_SLAVE_ADDR()		bfin_read16(TWI_SLAVE_ADDR)

#define bfin_write_TWI_SLAVE_ADDR(val)		bfin_write16(TWI_SLAVE_ADDR, val)

#define bfin_read_TWI_MASTER_CTL()		bfin_read16(TWI_MASTER_CTL)

#define bfin_write_TWI_MASTER_CTL(val)		bfin_write16(TWI_MASTER_CTL, val)

#define bfin_read_TWI_MASTER_STAT()		bfin_read16(TWI_MASTER_STAT)

#define bfin_write_TWI_MASTER_STAT(val)		bfin_write16(TWI_MASTER_STAT, val)

#define bfin_read_TWI_MASTER_ADDR()		bfin_read16(TWI_MASTER_ADDR)

#define bfin_write_TWI_MASTER_ADDR(val)		bfin_write16(TWI_MASTER_ADDR, val)

#define bfin_read_TWI_INT_STAT()		bfin_read16(TWI_INT_STAT)

#define bfin_write_TWI_INT_STAT(val)		bfin_write16(TWI_INT_STAT, val)

#define bfin_read_TWI_INT_MASK()		bfin_read16(TWI_INT_MASK)

#define bfin_write_TWI_INT_MASK(val)		bfin_write16(TWI_INT_MASK, val)

#define bfin_read_TWI_FIFO_CTL()		bfin_read16(TWI_FIFO_CTL)

#define bfin_write_TWI_FIFO_CTL(val)		bfin_write16(TWI_FIFO_CTL, val)

#define bfin_read_TWI_FIFO_STAT()		bfin_read16(TWI_FIFO_STAT)

#define bfin_write_TWI_FIFO_STAT(val)		bfin_write16(TWI_FIFO_STAT, val)

#define bfin_read_TWI_XMT_DATA8()		bfin_read16(TWI_XMT_DATA8)

#define bfin_write_TWI_XMT_DATA8(val)		bfin_write16(TWI_XMT_DATA8, val)

#define bfin_read_TWI_XMT_DATA16()		bfin_read16(TWI_XMT_DATA16)

#define bfin_write_TWI_XMT_DATA16(val)		bfin_write16(TWI_XMT_DATA16, val)

#define bfin_read_TWI_RCV_DATA8()		bfin_read16(TWI_RCV_DATA8)

#define bfin_write_TWI_RCV_DATA8(val)		bfin_write16(TWI_RCV_DATA8, val)

#define bfin_read_TWI_RCV_DATA16()		bfin_read16(TWI_RCV_DATA16)

#define bfin_write_TWI_RCV_DATA16(val)		bfin_write16(TWI_RCV_DATA16, val)







/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)								*/

/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)								*/

#define bfin_read_PORTGIO()			bfin_read16(PORTGIO)

#define bfin_read_PORTGIO()			bfin_read16(PORTGIO)

include/asm-blackfin/mach-bf537/cdefBF534.h

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@@ -859,38 +859,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) 
#define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)

#define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)





/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */

/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */

#define bfin_read_TWI_CLKDIV()               bfin_read16(TWI_CLKDIV)

#define bfin_write_TWI_CLKDIV(val)           bfin_write16(TWI_CLKDIV,val)

#define bfin_read_TWI_CONTROL()              bfin_read16(TWI_CONTROL)

#define bfin_write_TWI_CONTROL(val)          bfin_write16(TWI_CONTROL,val)

#define bfin_read_TWI_SLAVE_CTL()            bfin_read16(TWI_SLAVE_CTL)

#define bfin_write_TWI_SLAVE_CTL(val)        bfin_write16(TWI_SLAVE_CTL,val)

#define bfin_read_TWI_SLAVE_STAT()           bfin_read16(TWI_SLAVE_STAT)

#define bfin_write_TWI_SLAVE_STAT(val)       bfin_write16(TWI_SLAVE_STAT,val)

#define bfin_read_TWI_SLAVE_ADDR()           bfin_read16(TWI_SLAVE_ADDR)

#define bfin_write_TWI_SLAVE_ADDR(val)       bfin_write16(TWI_SLAVE_ADDR,val)

#define bfin_read_TWI_MASTER_CTL()           bfin_read16(TWI_MASTER_CTL)

#define bfin_write_TWI_MASTER_CTL(val)       bfin_write16(TWI_MASTER_CTL,val)

#define bfin_read_TWI_MASTER_STAT()          bfin_read16(TWI_MASTER_STAT)

#define bfin_write_TWI_MASTER_STAT(val)      bfin_write16(TWI_MASTER_STAT,val)

#define bfin_read_TWI_MASTER_ADDR()          bfin_read16(TWI_MASTER_ADDR)

#define bfin_write_TWI_MASTER_ADDR(val)      bfin_write16(TWI_MASTER_ADDR,val)

#define bfin_read_TWI_INT_STAT()             bfin_read16(TWI_INT_STAT)

#define bfin_write_TWI_INT_STAT(val)         bfin_write16(TWI_INT_STAT,val)

#define bfin_read_TWI_INT_MASK()             bfin_read16(TWI_INT_MASK)

#define bfin_write_TWI_INT_MASK(val)         bfin_write16(TWI_INT_MASK,val)

#define bfin_read_TWI_FIFO_CTL()             bfin_read16(TWI_FIFO_CTL)

#define bfin_write_TWI_FIFO_CTL(val)         bfin_write16(TWI_FIFO_CTL,val)

#define bfin_read_TWI_FIFO_STAT()            bfin_read16(TWI_FIFO_STAT)

#define bfin_write_TWI_FIFO_STAT(val)        bfin_write16(TWI_FIFO_STAT,val)

#define bfin_read_TWI_XMT_DATA8()            bfin_read16(TWI_XMT_DATA8)

#define bfin_write_TWI_XMT_DATA8(val)        bfin_write16(TWI_XMT_DATA8,val)

#define bfin_read_TWI_XMT_DATA16()           bfin_read16(TWI_XMT_DATA16)

#define bfin_write_TWI_XMT_DATA16(val)       bfin_write16(TWI_XMT_DATA16,val)

#define bfin_read_TWI_RCV_DATA8()            bfin_read16(TWI_RCV_DATA8)

#define bfin_write_TWI_RCV_DATA8(val)        bfin_write16(TWI_RCV_DATA8,val)

#define bfin_read_TWI_RCV_DATA16()           bfin_read16(TWI_RCV_DATA16)

#define bfin_write_TWI_RCV_DATA16(val)       bfin_write16(TWI_RCV_DATA16,val)





/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)								*/

/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)								*/

#define bfin_read_PORTGIO()                  bfin_read16(PORTGIO)

#define bfin_read_PORTGIO()                  bfin_read16(PORTGIO)

include/asm-blackfin/mach-bf548/cdefBF544.h

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@@ -113,39 +113,6 @@ 




/* Two Wire Interface Registers (TWI1) */

/* Two Wire Interface Registers (TWI1) */





#define bfin_read_TWI1_CLKDIV()			bfin_read16(TWI1_CLKDIV)

#define bfin_write_TWI1_CLKDIV(val)		bfin_write16(TWI1_CLKDIV, val)

#define bfin_read_TWI1_CONTROL()		bfin_read16(TWI1_CONTROL)

#define bfin_write_TWI1_CONTROL(val)		bfin_write16(TWI1_CONTROL, val)

#define bfin_read_TWI1_SLAVE_CTRL()		bfin_read16(TWI1_SLAVE_CTRL)

#define bfin_write_TWI1_SLAVE_CTRL(val)		bfin_write16(TWI1_SLAVE_CTRL, val)

#define bfin_read_TWI1_SLAVE_STAT()		bfin_read16(TWI1_SLAVE_STAT)

#define bfin_write_TWI1_SLAVE_STAT(val)		bfin_write16(TWI1_SLAVE_STAT, val)

#define bfin_read_TWI1_SLAVE_ADDR()		bfin_read16(TWI1_SLAVE_ADDR)

#define bfin_write_TWI1_SLAVE_ADDR(val)		bfin_write16(TWI1_SLAVE_ADDR, val)

#define bfin_read_TWI1_MASTER_CTRL()		bfin_read16(TWI1_MASTER_CTRL)

#define bfin_write_TWI1_MASTER_CTRL(val)	bfin_write16(TWI1_MASTER_CTRL, val)

#define bfin_read_TWI1_MASTER_STAT()		bfin_read16(TWI1_MASTER_STAT)

#define bfin_write_TWI1_MASTER_STAT(val)	bfin_write16(TWI1_MASTER_STAT, val)

#define bfin_read_TWI1_MASTER_ADDR()		bfin_read16(TWI1_MASTER_ADDR)

#define bfin_write_TWI1_MASTER_ADDR(val)	bfin_write16(TWI1_MASTER_ADDR, val)

#define bfin_read_TWI1_INT_STAT()		bfin_read16(TWI1_INT_STAT)

#define bfin_write_TWI1_INT_STAT(val)		bfin_write16(TWI1_INT_STAT, val)

#define bfin_read_TWI1_INT_MASK()		bfin_read16(TWI1_INT_MASK)

#define bfin_write_TWI1_INT_MASK(val)		bfin_write16(TWI1_INT_MASK, val)

#define bfin_read_TWI1_FIFO_CTRL()		bfin_read16(TWI1_FIFO_CTRL)

#define bfin_write_TWI1_FIFO_CTRL(val)		bfin_write16(TWI1_FIFO_CTRL, val)

#define bfin_read_TWI1_FIFO_STAT()		bfin_read16(TWI1_FIFO_STAT)

#define bfin_write_TWI1_FIFO_STAT(val)		bfin_write16(TWI1_FIFO_STAT, val)

#define bfin_read_TWI1_XMT_DATA8()		bfin_read16(TWI1_XMT_DATA8)

#define bfin_write_TWI1_XMT_DATA8(val)		bfin_write16(TWI1_XMT_DATA8, val)

#define bfin_read_TWI1_XMT_DATA16()		bfin_read16(TWI1_XMT_DATA16)

#define bfin_write_TWI1_XMT_DATA16(val)		bfin_write16(TWI1_XMT_DATA16, val)

#define bfin_read_TWI1_RCV_DATA8()		bfin_read16(TWI1_RCV_DATA8)

#define bfin_write_TWI1_RCV_DATA8(val)		bfin_write16(TWI1_RCV_DATA8, val)

#define bfin_read_TWI1_RCV_DATA16()		bfin_read16(TWI1_RCV_DATA16)

#define bfin_write_TWI1_RCV_DATA16(val)		bfin_write16(TWI1_RCV_DATA16, val)



/* CAN Controller 1 Config 1 Registers */

/* CAN Controller 1 Config 1 Registers */





#define bfin_read_CAN1_MC1()		bfin_read16(CAN1_MC1)

#define bfin_read_CAN1_MC1()		bfin_read16(CAN1_MC1)

include/asm-blackfin/mach-bf548/cdefBF547.h

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@@ -185,39 +185,6 @@ 




/* Two Wire Interface Registers (TWI1) */

/* Two Wire Interface Registers (TWI1) */





#define bfin_read_TWI1_CLKDIV()			bfin_read16(TWI1_CLKDIV)

#define bfin_write_TWI1_CLKDIV(val)		bfin_write16(TWI1_CLKDIV, val)

#define bfin_read_TWI1_CONTROL()		bfin_read16(TWI1_CONTROL)

#define bfin_write_TWI1_CONTROL(val)		bfin_write16(TWI1_CONTROL, val)

#define bfin_read_TWI1_SLAVE_CTRL()		bfin_read16(TWI1_SLAVE_CTRL)

#define bfin_write_TWI1_SLAVE_CTRL(val)		bfin_write16(TWI1_SLAVE_CTRL, val)

#define bfin_read_TWI1_SLAVE_STAT()		bfin_read16(TWI1_SLAVE_STAT)

#define bfin_write_TWI1_SLAVE_STAT(val)		bfin_write16(TWI1_SLAVE_STAT, val)

#define bfin_read_TWI1_SLAVE_ADDR()		bfin_read16(TWI1_SLAVE_ADDR)

#define bfin_write_TWI1_SLAVE_ADDR(val)		bfin_write16(TWI1_SLAVE_ADDR, val)

#define bfin_read_TWI1_MASTER_CTRL()		bfin_read16(TWI1_MASTER_CTRL)

#define bfin_write_TWI1_MASTER_CTRL(val)	bfin_write16(TWI1_MASTER_CTRL, val)

#define bfin_read_TWI1_MASTER_STAT()		bfin_read16(TWI1_MASTER_STAT)

#define bfin_write_TWI1_MASTER_STAT(val)	bfin_write16(TWI1_MASTER_STAT, val)

#define bfin_read_TWI1_MASTER_ADDR()		bfin_read16(TWI1_MASTER_ADDR)

#define bfin_write_TWI1_MASTER_ADDR(val)	bfin_write16(TWI1_MASTER_ADDR, val)

#define bfin_read_TWI1_INT_STAT()		bfin_read16(TWI1_INT_STAT)

#define bfin_write_TWI1_INT_STAT(val)		bfin_write16(TWI1_INT_STAT, val)

#define bfin_read_TWI1_INT_MASK()		bfin_read16(TWI1_INT_MASK)

#define bfin_write_TWI1_INT_MASK(val)		bfin_write16(TWI1_INT_MASK, val)

#define bfin_read_TWI1_FIFO_CTRL()		bfin_read16(TWI1_FIFO_CTRL)

#define bfin_write_TWI1_FIFO_CTRL(val)		bfin_write16(TWI1_FIFO_CTRL, val)

#define bfin_read_TWI1_FIFO_STAT()		bfin_read16(TWI1_FIFO_STAT)

#define bfin_write_TWI1_FIFO_STAT(val)		bfin_write16(TWI1_FIFO_STAT, val)

#define bfin_read_TWI1_XMT_DATA8()		bfin_read16(TWI1_XMT_DATA8)

#define bfin_write_TWI1_XMT_DATA8(val)		bfin_write16(TWI1_XMT_DATA8, val)

#define bfin_read_TWI1_XMT_DATA16()		bfin_read16(TWI1_XMT_DATA16)

#define bfin_write_TWI1_XMT_DATA16(val)		bfin_write16(TWI1_XMT_DATA16, val)

#define bfin_read_TWI1_RCV_DATA8()		bfin_read16(TWI1_RCV_DATA8)

#define bfin_write_TWI1_RCV_DATA8(val)		bfin_write16(TWI1_RCV_DATA8, val)

#define bfin_read_TWI1_RCV_DATA16()		bfin_read16(TWI1_RCV_DATA16)

#define bfin_write_TWI1_RCV_DATA16(val)		bfin_write16(TWI1_RCV_DATA16, val)



/* SPI2  Registers */

/* SPI2  Registers */





#define bfin_read_SPI2_CTL()		bfin_read16(SPI2_CTL)

#define bfin_read_SPI2_CTL()		bfin_read16(SPI2_CTL)

include/asm-blackfin/mach-bf548/cdefBF548.h

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@@ -185,39 +185,6 @@ 




/* Two Wire Interface Registers (TWI1) */

/* Two Wire Interface Registers (TWI1) */





#define bfin_read_TWI1_CLKDIV()			bfin_read16(TWI1_CLKDIV)

#define bfin_write_TWI1_CLKDIV(val)		bfin_write16(TWI1_CLKDIV, val)

#define bfin_read_TWI1_CONTROL()		bfin_read16(TWI1_CONTROL)

#define bfin_write_TWI1_CONTROL(val)		bfin_write16(TWI1_CONTROL, val)

#define bfin_read_TWI1_SLAVE_CTRL()		bfin_read16(TWI1_SLAVE_CTRL)

#define bfin_write_TWI1_SLAVE_CTRL(val)		bfin_write16(TWI1_SLAVE_CTRL, val)

#define bfin_read_TWI1_SLAVE_STAT()		bfin_read16(TWI1_SLAVE_STAT)

#define bfin_write_TWI1_SLAVE_STAT(val)		bfin_write16(TWI1_SLAVE_STAT, val)

#define bfin_read_TWI1_SLAVE_ADDR()		bfin_read16(TWI1_SLAVE_ADDR)

#define bfin_write_TWI1_SLAVE_ADDR(val)		bfin_write16(TWI1_SLAVE_ADDR, val)

#define bfin_read_TWI1_MASTER_CTRL()		bfin_read16(TWI1_MASTER_CTRL)

#define bfin_write_TWI1_MASTER_CTRL(val)	bfin_write16(TWI1_MASTER_CTRL, val)

#define bfin_read_TWI1_MASTER_STAT()		bfin_read16(TWI1_MASTER_STAT)

#define bfin_write_TWI1_MASTER_STAT(val)	bfin_write16(TWI1_MASTER_STAT, val)

#define bfin_read_TWI1_MASTER_ADDR()		bfin_read16(TWI1_MASTER_ADDR)

#define bfin_write_TWI1_MASTER_ADDR(val)	bfin_write16(TWI1_MASTER_ADDR, val)

#define bfin_read_TWI1_INT_STAT()		bfin_read16(TWI1_INT_STAT)

#define bfin_write_TWI1_INT_STAT(val)		bfin_write16(TWI1_INT_STAT, val)

#define bfin_read_TWI1_INT_MASK()		bfin_read16(TWI1_INT_MASK)

#define bfin_write_TWI1_INT_MASK(val)		bfin_write16(TWI1_INT_MASK, val)

#define bfin_read_TWI1_FIFO_CTRL()		bfin_read16(TWI1_FIFO_CTRL)

#define bfin_write_TWI1_FIFO_CTRL(val)		bfin_write16(TWI1_FIFO_CTRL, val)

#define bfin_read_TWI1_FIFO_STAT()		bfin_read16(TWI1_FIFO_STAT)

#define bfin_write_TWI1_FIFO_STAT(val)		bfin_write16(TWI1_FIFO_STAT, val)

#define bfin_read_TWI1_XMT_DATA8()		bfin_read16(TWI1_XMT_DATA8)

#define bfin_write_TWI1_XMT_DATA8(val)		bfin_write16(TWI1_XMT_DATA8, val)

#define bfin_read_TWI1_XMT_DATA16()		bfin_read16(TWI1_XMT_DATA16)

#define bfin_write_TWI1_XMT_DATA16(val)		bfin_write16(TWI1_XMT_DATA16, val)

#define bfin_read_TWI1_RCV_DATA8()		bfin_read16(TWI1_RCV_DATA8)

#define bfin_write_TWI1_RCV_DATA8(val)		bfin_write16(TWI1_RCV_DATA8, val)

#define bfin_read_TWI1_RCV_DATA16()		bfin_read16(TWI1_RCV_DATA16)

#define bfin_write_TWI1_RCV_DATA16(val)		bfin_write16(TWI1_RCV_DATA16, val)



/* SPI2  Registers */

/* SPI2  Registers */





#define bfin_read_SPI2_CTL()		bfin_read16(SPI2_CTL)

#define bfin_read_SPI2_CTL()		bfin_read16(SPI2_CTL)