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Commit b529e921 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Greg Kroah-Hartman
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drm/msm/dsi_pll_10nm: restore VCO rate during restore_state 



[ Upstream commit a4ccc37693a271330a46208afbeaed939d54fdbb ]

PHY disable/enable resets PLL registers to default values. Thus in
addition to restoring several registers we also need to restore VCO rate
settings.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: c6659785dfb3 ("drm/msm/dsi/pll: call vco set rate explicitly")
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent dc8805b8

drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c

+8 −0
Original line number Diff line number Diff line
@@ -554,6 +554,7 @@ static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll) 
	struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;

	void __iomem *phy_base = pll_10nm->phy_cmn_mmio;

	u32 val;

	int ret;



	val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);

	val &= ~0x3;
@@ -568,6 +569,13 @@ static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll) 
	val |= cached->pll_mux;

	pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);



	ret = dsi_pll_10nm_vco_set_rate(&pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);

	if (ret) {

		DRM_DEV_ERROR(&pll_10nm->pdev->dev,

			"restore vco rate failed. ret=%d\n", ret);

		return ret;

	}



	DBG("DSI PLL%d", pll_10nm->id);



	return 0;