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Commit b5136524 authored by Chanwoo Choi's avatar Chanwoo Choi Committed by MyungJoo Ham
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PM / devfreq: exynos-bus: Add the detailed correlation for Exynos5433 



This patch adds the detailed corrleation between sub-blocks and VDD_INT power
line for Exynos5433. VDD_INT provided the power source to INT (Internal) block.

Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarMyungJoo Ham <myungjoo.ham@samsung.com>
parent 924b9111

Documentation/devicetree/bindings/devfreq/exynos-bus.txt

+14 −0
Original line number Original line Diff line number Diff line
@@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC: 
		|--- FSYS

		|--- FSYS

		|--- FSYS2

		|--- FSYS2





- In case of Exynos5433, there is VDD_INT power line as following:

	VDD_INT |--- G2D (parent device)

		|--- MSCL

		|--- GSCL

		|--- JPEG

		|--- MFC

		|--- HEVC

		|--- BUS0

		|--- BUS1

		|--- BUS2

		|--- PERIS (Fixed clock rate)

		|--- PERIC (Fixed clock rate)

		|--- FSYS  (Fixed clock rate)



Example1:

Example1:

	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to

	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to

	power line (regulator). The MIF (Memory Interface) AXI bus is used to

	power line (regulator). The MIF (Memory Interface) AXI bus is used to