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Commit b4bb68f7 authored by Bernd Schmidt's avatar Bernd Schmidt Committed by Bryan Wu
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[Blackfin] arch: fix bug - Make the MPU code aware of the async banks and the uncached DMA area. 

Bug: CONFIG_MPU doesn't seem to handle access to ASYNC/IO Memory well
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3912



Signed-off-by: default avatarBernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 2a0c4fdb

arch/blackfin/kernel/cplb-mpu/cplbmgr.c

+27 −19
Original line number Original line Diff line number Diff line
@@ -143,16 +143,25 @@ static noinline int dcplb_miss(void) 
	unsigned long d_data;

	unsigned long d_data;





	nr_dcplb_miss++;

	nr_dcplb_miss++;

	if (addr >= _ramend)

		return CPLB_PROT_VIOL;





	d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;

	d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;

#ifdef CONFIG_BFIN_DCACHE

#ifdef CONFIG_BFIN_DCACHE

	if (addr < _ramend - DMA_UNCACHED_REGION) {

		d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;

		d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;

#ifdef CONFIG_BFIN_WT

#ifdef CONFIG_BFIN_WT

		d_data |= CPLB_L1_AOW | CPLB_WT;

		d_data |= CPLB_L1_AOW | CPLB_WT;

#endif

#endif

	}

#endif

#endif

	if (addr >= _ramend) {

		if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE

		    && (status & FAULT_USERSUPV)) {

			addr &= ~0x3fffff;

			d_data &= ~PAGE_SIZE_4KB;

			d_data |= PAGE_SIZE_4MB;

		} else

			return CPLB_PROT_VIOL;

	} else {

		mask = current_rwx_mask;

		mask = current_rwx_mask;

		if (mask) {

		if (mask) {

			int page = addr >> PAGE_SHIFT;

			int page = addr >> PAGE_SHIFT;
@@ -166,7 +175,7 @@ static noinline int dcplb_miss(void) 
			if (mask[offs] & bit)

			if (mask[offs] & bit)

				d_data |= CPLB_USER_WR;

				d_data |= CPLB_USER_WR;

		}

		}



	}

	idx = evict_one_dcplb();

	idx = evict_one_dcplb();





	addr &= PAGE_MASK;

	addr &= PAGE_MASK;
@@ -281,7 +290,6 @@ int cplb_hdr(int seqstat, struct pt_regs *regs) 
		return dcplb_miss();

		return dcplb_miss();

	default:

	default:

		return 1;

		return 1;

		panic_cplb_error(seqstat, regs);

	}

	}

}

}