[media] v4l: omap4iss: Add support for OMAP4 camera interface - CSI receivers

/*

 * TI OMAP4 ISS V4L2 Driver - CSI2 module

 *

 * Copyright (C) 2012 Texas Instruments, Inc.

 *

 * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */

#ifndef OMAP4_ISS_CSI2_H

#define OMAP4_ISS_CSI2_H

#include <linux/types.h>

#include <linux/videodev2.h>

#include "iss_video.h"

struct iss_csiphy;

/* This is not an exhaustive list */

enum iss_csi2_pix_formats {

	CSI2_PIX_FMT_OTHERS = 0,

	CSI2_PIX_FMT_YUV422_8BIT = 0x1e,

	CSI2_PIX_FMT_YUV422_8BIT_VP = 0x9e,

	CSI2_PIX_FMT_YUV422_8BIT_VP16 = 0xde,

	CSI2_PIX_FMT_RAW10_EXP16 = 0xab,

	CSI2_PIX_FMT_RAW10_EXP16_VP = 0x12f,

	CSI2_PIX_FMT_RAW8 = 0x2a,

	CSI2_PIX_FMT_RAW8_DPCM10_EXP16 = 0x2aa,

	CSI2_PIX_FMT_RAW8_DPCM10_VP = 0x32a,

	CSI2_PIX_FMT_RAW8_VP = 0x12a,

	CSI2_USERDEF_8BIT_DATA1_DPCM10_VP = 0x340,

	CSI2_USERDEF_8BIT_DATA1_DPCM10 = 0x2c0,

	CSI2_USERDEF_8BIT_DATA1 = 0x40,

};

enum iss_csi2_irqevents {

	OCP_ERR_IRQ = 0x4000,

	SHORT_PACKET_IRQ = 0x2000,

	ECC_CORRECTION_IRQ = 0x1000,

	ECC_NO_CORRECTION_IRQ = 0x800,

	COMPLEXIO2_ERR_IRQ = 0x400,

	COMPLEXIO1_ERR_IRQ = 0x200,

	FIFO_OVF_IRQ = 0x100,

	CONTEXT7 = 0x80,

	CONTEXT6 = 0x40,

	CONTEXT5 = 0x20,

	CONTEXT4 = 0x10,

	CONTEXT3 = 0x8,

	CONTEXT2 = 0x4,

	CONTEXT1 = 0x2,

	CONTEXT0 = 0x1,

};

enum iss_csi2_ctx_irqevents {

	CTX_ECC_CORRECTION = 0x100,

	CTX_LINE_NUMBER = 0x80,

	CTX_FRAME_NUMBER = 0x40,

	CTX_CS = 0x20,

	CTX_LE = 0x8,

	CTX_LS = 0x4,

	CTX_FE = 0x2,

	CTX_FS = 0x1,

};

enum iss_csi2_frame_mode {

	ISS_CSI2_FRAME_IMMEDIATE,

	ISS_CSI2_FRAME_AFTERFEC,

};

#define ISS_CSI2_MAX_CTX_NUM	7

struct iss_csi2_ctx_cfg {

	u8 ctxnum;		/* context number 0 - 7 */

	u8 dpcm_decompress;

	/* Fields in CSI2_CTx_CTRL2 - locked by CSI2_CTx_CTRL1.CTX_EN */

	u8 virtual_id;

	u16 format_id;		/* as in CSI2_CTx_CTRL2[9:0] */

	u8 dpcm_predictor;	/* 1: simple, 0: advanced */

	/* Fields in CSI2_CTx_CTRL1/3 - Shadowed */

	u16 alpha;

	u16 data_offset;

	u32 ping_addr;

	u32 pong_addr;

	u8 eof_enabled;

	u8 eol_enabled;

	u8 checksum_enabled;

	u8 enabled;

};

struct iss_csi2_timing_cfg {

	u8 ionum;			/* IO1 or IO2 as in CSI2_TIMING */

	unsigned force_rx_mode:1;

	unsigned stop_state_16x:1;

	unsigned stop_state_4x:1;

	u16 stop_state_counter;

};

struct iss_csi2_ctrl_cfg {

	bool vp_clk_enable;

	bool vp_only_enable;

	u8 vp_out_ctrl;

	enum iss_csi2_frame_mode frame_mode;

	bool ecc_enable;

	bool if_enable;

};

#define CSI2_PAD_SINK		0

#define CSI2_PAD_SOURCE		1

#define CSI2_PADS_NUM		2

#define CSI2_OUTPUT_IPIPEIF	(1 << 0)

#define CSI2_OUTPUT_MEMORY	(1 << 1)

struct iss_csi2_device {

	struct v4l2_subdev subdev;

	struct media_pad pads[CSI2_PADS_NUM];

	struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];

	struct iss_video video_out;

	struct iss_device *iss;

	u8 available;		/* Is the IP present on the silicon? */

	/* Pointer to register remaps into kernel space */

	void __iomem *regs1;

	void __iomem *regs2;

	u32 output; /* output to IPIPEIF, memory or both? */

	bool dpcm_decompress;

	unsigned int frame_skip;

	bool use_fs_irq;

	struct iss_csiphy *phy;

	struct iss_csi2_ctx_cfg contexts[ISS_CSI2_MAX_CTX_NUM + 1];

	struct iss_csi2_timing_cfg timing[2];

	struct iss_csi2_ctrl_cfg ctrl;

	enum iss_pipeline_stream_state state;

	wait_queue_head_t wait;

	atomic_t stopping;

};

void omap4iss_csi2_isr(struct iss_csi2_device *csi2);

int omap4iss_csi2_reset(struct iss_csi2_device *csi2);

int omap4iss_csi2_init(struct iss_device *iss);

void omap4iss_csi2_cleanup(struct iss_device *iss);

void omap4iss_csi2_unregister_entities(struct iss_csi2_device *csi2);

int omap4iss_csi2_register_entities(struct iss_csi2_device *csi2,

				    struct v4l2_device *vdev);

#endif	/* OMAP4_ISS_CSI2_H */

/*

 * TI OMAP4 ISS V4L2 Driver - CSI PHY module

 *

 * Copyright (C) 2012 Texas Instruments, Inc.

 *

 * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */

#include <linux/delay.h>

#include <linux/device.h>

#include "../../../../arch/arm/mach-omap2/control.h"

#include "iss.h"

#include "iss_regs.h"

#include "iss_csiphy.h"

/*

 * csiphy_lanes_config - Configuration of CSIPHY lanes.

 *

 * Updates HW configuration.

 * Called with phy->mutex taken.

 */

static void csiphy_lanes_config(struct iss_csiphy *phy)

{

	unsigned int i;

	u32 reg;

	reg = readl(phy->cfg_regs + CSI2_COMPLEXIO_CFG);

	for (i = 0; i < phy->max_data_lanes; i++) {

		reg &= ~(CSI2_COMPLEXIO_CFG_DATA_POL(i + 1) |

			 CSI2_COMPLEXIO_CFG_DATA_POSITION_MASK(i + 1));

		reg |= (phy->lanes.data[i].pol ?

			CSI2_COMPLEXIO_CFG_DATA_POL(i + 1) : 0);

		reg |= (phy->lanes.data[i].pos <<

			CSI2_COMPLEXIO_CFG_DATA_POSITION_SHIFT(i + 1));

	}

	reg &= ~(CSI2_COMPLEXIO_CFG_CLOCK_POL |

		 CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK);

	reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0;

	reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT;

	writel(reg, phy->cfg_regs + CSI2_COMPLEXIO_CFG);

}

/*

 * csiphy_set_power

 * @power: Power state to be set.

 *

 * Returns 0 if successful, or -EBUSY if the retry count is exceeded.

 */

static int csiphy_set_power(struct iss_csiphy *phy, u32 power)

{

	u32 reg;

	u8 retry_count;

	writel((readl(phy->cfg_regs + CSI2_COMPLEXIO_CFG) &

		~CSI2_COMPLEXIO_CFG_PWD_CMD_MASK) |

		power,

		phy->cfg_regs + CSI2_COMPLEXIO_CFG);

	retry_count = 0;

	do {

		udelay(1);

		reg = readl(phy->cfg_regs + CSI2_COMPLEXIO_CFG) &

				CSI2_COMPLEXIO_CFG_PWD_STATUS_MASK;

		if (reg != power >> 2)

			retry_count++;

	} while ((reg != power >> 2) && (retry_count < 250));

	if (retry_count == 250) {

		printk(KERN_ERR "CSI2 CIO set power failed!\n");

		return -EBUSY;

	}

	return 0;

}

/*

 * csiphy_dphy_config - Configure CSI2 D-PHY parameters.

 *

 * Called with phy->mutex taken.

 */

static void csiphy_dphy_config(struct iss_csiphy *phy)

{

	u32 reg;

	/* Set up REGISTER0 */

	reg = phy->dphy.ths_term << REGISTER0_THS_TERM_SHIFT;

	reg |= phy->dphy.ths_settle << REGISTER0_THS_SETTLE_SHIFT;

	writel(reg, phy->phy_regs + REGISTER0);

	/* Set up REGISTER1 */

	reg = phy->dphy.tclk_term << REGISTER1_TCLK_TERM_SHIFT;

	reg |= phy->dphy.tclk_miss << REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT;

	reg |= phy->dphy.tclk_settle << REGISTER1_TCLK_SETTLE_SHIFT;

	reg |= 0xB8 << REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT;

	writel(reg, phy->phy_regs + REGISTER1);

}

/*

 * TCLK values are OK at their reset values

 */

#define TCLK_TERM	0

#define TCLK_MISS	1

#define TCLK_SETTLE	14

int omap4iss_csiphy_config(struct iss_device *iss,

			   struct v4l2_subdev *csi2_subdev)

{

	struct iss_csi2_device *csi2 = v4l2_get_subdevdata(csi2_subdev);

	struct iss_pipeline *pipe = to_iss_pipeline(&csi2_subdev->entity);

	struct iss_v4l2_subdevs_group *subdevs = pipe->external->host_priv;

	struct iss_csiphy_dphy_cfg csi2phy;

	int csi2_ddrclk_khz;

	struct iss_csiphy_lanes_cfg *lanes;

	unsigned int used_lanes = 0;

	u32 cam_rx_ctrl;

	unsigned int i;

	lanes = &subdevs->bus.csi2.lanecfg;

	/*

	 * SCM.CONTROL_CAMERA_RX

	 * - bit [31] : CSIPHY2 lane 2 enable (4460+ only)

	 * - bit [30:29] : CSIPHY2 per-lane enable (1 to 0)

	 * - bit [28:24] : CSIPHY1 per-lane enable (4 to 0)

	 * - bit [21] : CSIPHY2 CTRLCLK enable

	 * - bit [20:19] : CSIPHY2 config: 00 d-phy, 01/10 ccp2

	 * - bit [18] : CSIPHY1 CTRLCLK enable

	 * - bit [17:16] : CSIPHY1 config: 00 d-phy, 01/10 ccp2

	 */

	cam_rx_ctrl = omap4_ctrl_pad_readl(

			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX);

	if (subdevs->interface == ISS_INTERFACE_CSI2A_PHY1) {

		cam_rx_ctrl &= ~(OMAP4_CAMERARX_CSI21_LANEENABLE_MASK |

				OMAP4_CAMERARX_CSI21_CAMMODE_MASK);

		/* NOTE: Leave CSIPHY1 config to 0x0: D-PHY mode */

		/* Enable all lanes for now */

		cam_rx_ctrl |=

			0x1F << OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT;

		/* Enable CTRLCLK */

		cam_rx_ctrl |= OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK;

	}

	if (subdevs->interface == ISS_INTERFACE_CSI2B_PHY2) {

		cam_rx_ctrl &= ~(OMAP4_CAMERARX_CSI22_LANEENABLE_MASK |

				OMAP4_CAMERARX_CSI22_CAMMODE_MASK);

		/* NOTE: Leave CSIPHY2 config to 0x0: D-PHY mode */

		/* Enable all lanes for now */

		cam_rx_ctrl |=

			0x3 << OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT;

		/* Enable CTRLCLK */

		cam_rx_ctrl |= OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK;

	}

	omap4_ctrl_pad_writel(cam_rx_ctrl,

		 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX);

	/* Reset used lane count */

	csi2->phy->used_data_lanes = 0;

	/* Clock and data lanes verification */

	for (i = 0; i < csi2->phy->max_data_lanes; i++) {

		if (lanes->data[i].pos == 0)

			continue;

		if (lanes->data[i].pol > 1 || lanes->data[i].pos > (csi2->phy->max_data_lanes + 1))

			return -EINVAL;

		if (used_lanes & (1 << lanes->data[i].pos))

			return -EINVAL;

		used_lanes |= 1 << lanes->data[i].pos;

		csi2->phy->used_data_lanes++;

	}

	if (lanes->clk.pol > 1 || lanes->clk.pos > (csi2->phy->max_data_lanes + 1))

		return -EINVAL;

	if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos))

		return -EINVAL;

	csi2_ddrclk_khz = pipe->external_rate / 1000

		/ (2 * csi2->phy->used_data_lanes)

		* pipe->external_bpp;

	/*

	 * THS_TERM: Programmed value = ceil(12.5 ns/DDRClk period) - 1.

	 * THS_SETTLE: Programmed value = ceil(90 ns/DDRClk period) + 3.

	 */

	csi2phy.ths_term = DIV_ROUND_UP(25 * csi2_ddrclk_khz, 2000000) - 1;

	csi2phy.ths_settle = DIV_ROUND_UP(90 * csi2_ddrclk_khz, 1000000) + 3;

	csi2phy.tclk_term = TCLK_TERM;

	csi2phy.tclk_miss = TCLK_MISS;

	csi2phy.tclk_settle = TCLK_SETTLE;

	mutex_lock(&csi2->phy->mutex);

	csi2->phy->dphy = csi2phy;

	csi2->phy->lanes = *lanes;

	mutex_unlock(&csi2->phy->mutex);

	return 0;

}

int omap4iss_csiphy_acquire(struct iss_csiphy *phy)

{

	int rval;

	mutex_lock(&phy->mutex);

	rval = omap4iss_csi2_reset(phy->csi2);

	if (rval)

		goto done;

	csiphy_dphy_config(phy);

	csiphy_lanes_config(phy);

	rval = csiphy_set_power(phy, CSI2_COMPLEXIO_CFG_PWD_CMD_ON);

	if (rval)

		goto done;

	phy->phy_in_use = 1;

done:

	mutex_unlock(&phy->mutex);

	return rval;

}

void omap4iss_csiphy_release(struct iss_csiphy *phy)

{

	mutex_lock(&phy->mutex);

	if (phy->phy_in_use) {

		csiphy_set_power(phy, CSI2_COMPLEXIO_CFG_PWD_CMD_OFF);

		phy->phy_in_use = 0;

	}

	mutex_unlock(&phy->mutex);

}

/*

 * omap4iss_csiphy_init - Initialize the CSI PHY frontends

 */

int omap4iss_csiphy_init(struct iss_device *iss)

{

	struct iss_csiphy *phy1 = &iss->csiphy1;

	struct iss_csiphy *phy2 = &iss->csiphy2;

	phy1->iss = iss;

	phy1->csi2 = &iss->csi2a;

	phy1->max_data_lanes = ISS_CSIPHY1_NUM_DATA_LANES;

	phy1->used_data_lanes = 0;

	phy1->cfg_regs = iss->regs[OMAP4_ISS_MEM_CSI2_A_REGS1];

	phy1->phy_regs = iss->regs[OMAP4_ISS_MEM_CAMERARX_CORE1];

	mutex_init(&phy1->mutex);

	phy2->iss = iss;

	phy2->csi2 = &iss->csi2b;

	phy2->max_data_lanes = ISS_CSIPHY2_NUM_DATA_LANES;

	phy2->used_data_lanes = 0;

	phy2->cfg_regs = iss->regs[OMAP4_ISS_MEM_CSI2_B_REGS1];

	phy2->phy_regs = iss->regs[OMAP4_ISS_MEM_CAMERARX_CORE2];

	mutex_init(&phy2->mutex);

	return 0;

}

/*

 * TI OMAP4 ISS V4L2 Driver - CSI PHY module

 *

 * Copyright (C) 2012 Texas Instruments, Inc.

 *

 * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */

#ifndef OMAP4_ISS_CSI_PHY_H

#define OMAP4_ISS_CSI_PHY_H

#include <media/omap4iss.h>

struct iss_csi2_device;

struct iss_csiphy_dphy_cfg {

	u8 ths_term;

	u8 ths_settle;

	u8 tclk_term;

	unsigned tclk_miss:1;

	u8 tclk_settle;

};

struct iss_csiphy {

	struct iss_device *iss;

	struct mutex mutex;	/* serialize csiphy configuration */

	u8 phy_in_use;

	struct iss_csi2_device *csi2;

	/* Pointer to register remaps into kernel space */

	void __iomem *cfg_regs;

	void __iomem *phy_regs;

	u8 max_data_lanes;	/* number of CSI2 Data Lanes supported */

	u8 used_data_lanes;	/* number of CSI2 Data Lanes used */

	struct iss_csiphy_lanes_cfg lanes;

	struct iss_csiphy_dphy_cfg dphy;

};

int omap4iss_csiphy_config(struct iss_device *iss,

			   struct v4l2_subdev *csi2_subdev);

int omap4iss_csiphy_acquire(struct iss_csiphy *phy);

void omap4iss_csiphy_release(struct iss_csiphy *phy);

int omap4iss_csiphy_init(struct iss_device *iss);

#endif	/* OMAP4_ISS_CSI_PHY_H */