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Commit b3e6c0e4 authored by Vishal Verma's avatar Vishal Verma
Browse files

ARM: dts: msm: Add tpg node to bengal device tree

The tpg node is added with mandatory parameters
to bengal device tree to be probed as different
camera ID.

CRs-Fixed: 2943036
External Impact: No.

Change-Id: Ic5d10d388cadf942d8105c89a9af795cc9e9355b
parent 686ffd5a
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+69 −0
Original line number Diff line number Diff line
@@ -398,4 +398,73 @@
		clock-cntl-level = "turbo";
		clock-rates = <19200000>;
	};

	/*TPG0*/
	qcom,cam-tpg0 {
		cell-index = <4>;
		compatible = "qcom,cam-sensor";
		csiphy-sd-index = <4>;
		sensor-position-roll = <270>;
		sensor-position-pitch = <0>;
		sensor-position-yaw = <180>;
		gpios = <&tlmm 30 0>,
			<&tlmm 35 0>;
		gpio-reset = <1>;
		gpio-req-tbl-num = <0 1>;
		gpio-req-tbl-flags = <1 0>;
		gpio-req-tbl-label = "CAMIF_MCLK1",
					"CAM_RESET1";
		sensor-mode = <0>;
		status = "ok";
		clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
		clock-names = "cam_clk";
		clock-cntl-level = "turbo";
		clock-rates = <19200000>;
	};

	/*TPG1*/
	qcom,cam-tpg1 {
		cell-index = <5>;
		compatible = "qcom,cam-sensor";
		csiphy-sd-index = <5>;
		sensor-position-roll = <270>;
		sensor-position-pitch = <0>;
		sensor-position-yaw = <180>;
		gpios = <&tlmm 30 0>,
			<&tlmm 35 0>;
		gpio-reset = <1>;
		gpio-req-tbl-num = <0 1>;
		gpio-req-tbl-flags = <1 0>;
		gpio-req-tbl-label = "CAMIF_MCLK1",
					"CAM_RESET1";
		sensor-mode = <0>;
		status = "ok";
		clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
		clock-names = "cam_clk";
		clock-cntl-level = "turbo";
		clock-rates = <19200000>;
	};

	/*TPG2*/
	qcom,cam-tpg2 {
		cell-index = <6>;
		compatible = "qcom,cam-sensor";
		csiphy-sd-index = <6>;
		sensor-position-roll = <270>;
		sensor-position-pitch = <0>;
		sensor-position-yaw = <180>;
		gpios = <&tlmm 30 0>,
			<&tlmm 35 0>;
		gpio-reset = <1>;
		gpio-req-tbl-num = <0 1>;
		gpio-req-tbl-flags = <1 0>;
		gpio-req-tbl-label = "CAMIF_MCLK1",
					"CAM_RESET1";
		sensor-mode = <0>;
		status = "ok";
		clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
		clock-names = "cam_clk";
		clock-cntl-level = "turbo";
		clock-rates = <19200000>;
	};
};