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Commit b3e62463 authored by Stephane Eranian's avatar Stephane Eranian Committed by Ingo Molnar
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perf/x86/pebs: Add proper PEBS constraints for Broadwell 



This patch adds a Broadwell specific PEBS event constraint table.

Broadwell has a fix for the HT corruption bug erratum HSD29 on
Haswell. Therefore, there is no need to mark events 0xd0, 0xd1, 0xd2,
0xd3 has requiring the exclusive mode across both sibling HT threads.
This holds true for regular counting and sampling (see core.c) and
PEBS (ds.c) which we fix in this patch.

In doing so, we relax evnt scheduling for these events, they can now
be programmed on any 4 counters without impacting what is measured on
the sibling thread.

Signed-off-by: default avatarStephane Eranian <eranian@google.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: acme@redhat.com
Cc: adrian.hunter@intel.com
Cc: jolsa@redhat.com
Cc: kan.liang@intel.com
Cc: namhyung@kernel.org
Link: http://lkml.kernel.org/r/1457034642-21837-4-git-send-email-eranian@google.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 8077eca0

arch/x86/events/intel/core.c

+1 −1
Original line number Diff line number Diff line
@@ -3602,7 +3602,7 @@ __init int intel_pmu_init(void) 
		intel_pmu_lbr_init_hsw();



		x86_pmu.event_constraints = intel_bdw_event_constraints;

		x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;

		x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;

		x86_pmu.extra_regs = intel_snbep_extra_regs;

		x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;

		x86_pmu.pebs_prec_dist = true;

arch/x86/events/intel/ds.c

+24 −0
Original line number Diff line number Diff line
@@ -722,6 +722,30 @@ struct event_constraint intel_hsw_pebs_event_constraints[] = { 
	EVENT_CONSTRAINT_END

};



struct event_constraint intel_bdw_pebs_event_constraints[] = {

	INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */

	INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */

	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */

	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),

	/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */

	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */

	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */

	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */

	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */

	/* Allow all events as PEBS with no flags */

	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),

	EVENT_CONSTRAINT_END

};





struct event_constraint intel_skl_pebs_event_constraints[] = {

	INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),	/* INST_RETIRED.PREC_DIST */

	/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */

arch/x86/events/perf_event.h

+2 −0
Original line number Diff line number Diff line
@@ -861,6 +861,8 @@ extern struct event_constraint intel_ivb_pebs_event_constraints[]; 


extern struct event_constraint intel_hsw_pebs_event_constraints[];



extern struct event_constraint intel_bdw_pebs_event_constraints[];



extern struct event_constraint intel_skl_pebs_event_constraints[];



struct event_constraint *intel_pebs_constraints(struct perf_event *event);