Merge "i2c-qcom-geni: Handle the DMA transfer complete interrupt" (b3984317) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/i2c/busses/i2c-qcom-geni.c

+7 −3

Original line number	Original line	Diff line number	Diff line
	@@ -321,11 +321,12 @@ static irqreturn_t geni_i2c_irq(int irq, void *dev)
	SE_DMA_RX_IRQ_CLR);		SE_DMA_RX_IRQ_CLR);
	/* Ensure all writes are done before returning from ISR. */		/* Ensure all writes are done before returning from ISR. */
	wmb();		wmb();
			if ((dm_tx_st & TX_DMA_DONE) \|\| (dm_rx_st & RX_DMA_DONE))
			complete(&gi2c->xfer);

	}		}
	/* if this is err with done-bit not set, handle that thr' timeout. */		/* if this is err with done-bit not set, handle that thr' timeout. */
	if (m_stat & M_CMD_DONE_EN)		else if (m_stat & M_CMD_DONE_EN)
	complete(&gi2c->xfer);
	else if ((dm_tx_st & TX_DMA_DONE) \|\| (dm_rx_st & RX_DMA_DONE))
	complete(&gi2c->xfer);		complete(&gi2c->xfer);

	return IRQ_HANDLED;		return IRQ_HANDLED;
	@@ -665,6 +666,7 @@ static int geni_i2c_xfer(struct i2c_adapter *adap,
	dma_addr_t tx_dma = 0;		dma_addr_t tx_dma = 0;
	dma_addr_t rx_dma = 0;		dma_addr_t rx_dma = 0;
	enum se_xfer_mode mode = FIFO_MODE;		enum se_xfer_mode mode = FIFO_MODE;
			reinit_completion(&gi2c->xfer);

	m_param \|= (stretch ? STOP_STRETCH : 0);		m_param \|= (stretch ? STOP_STRETCH : 0);
	m_param \|= ((msgs[i].addr & 0x7F) << SLV_ADDR_SHFT);		m_param \|= ((msgs[i].addr & 0x7F) << SLV_ADDR_SHFT);
	@@ -724,6 +726,7 @@ static int geni_i2c_xfer(struct i2c_adapter *adap,
	gi2c->xfer_timeout);		gi2c->xfer_timeout);
	if (!timeout) {		if (!timeout) {
	geni_i2c_err(gi2c, GENI_TIMEOUT);		geni_i2c_err(gi2c, GENI_TIMEOUT);
			reinit_completion(&gi2c->xfer);
	gi2c->cur = NULL;		gi2c->cur = NULL;
	geni_abort_m_cmd(gi2c->base);		geni_abort_m_cmd(gi2c->base);
	timeout = wait_for_completion_timeout(&gi2c->xfer, HZ);		timeout = wait_for_completion_timeout(&gi2c->xfer, HZ);
	@@ -732,6 +735,7 @@ static int geni_i2c_xfer(struct i2c_adapter *adap,
	gi2c->cur_rd = 0;		gi2c->cur_rd = 0;
	if (mode == SE_DMA) {		if (mode == SE_DMA) {
	if (gi2c->err) {		if (gi2c->err) {
			reinit_completion(&gi2c->xfer);
	if (msgs[i].flags != I2C_M_RD)		if (msgs[i].flags != I2C_M_RD)
	writel_relaxed(1, gi2c->base +		writel_relaxed(1, gi2c->base +
	SE_DMA_TX_FSM_RST);		SE_DMA_TX_FSM_RST);

drivers/platform/msm/qcom-geni-se.c

+6 −8

Original line number	Original line	Diff line number	Diff line
	@@ -290,6 +290,10 @@ static int geni_se_select_fifo_mode(void __iomem *base)
	geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR);		geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR);
	geni_write_reg(0xFFFFFFFF, base, SE_IRQ_EN);		geni_write_reg(0xFFFFFFFF, base, SE_IRQ_EN);

			/* Clearing registers before reading */
			geni_write_reg(0x00000000, base, SE_GENI_M_IRQ_EN);
			geni_write_reg(0x00000000, base, SE_GENI_S_IRQ_EN);

	common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN);		common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN);
	common_geni_s_irq_en = geni_read_reg(base, SE_GENI_S_IRQ_EN);		common_geni_s_irq_en = geni_read_reg(base, SE_GENI_S_IRQ_EN);
	geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN);		geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN);
	@@ -309,9 +313,7 @@ static int geni_se_select_fifo_mode(void __iomem *base)

	static int geni_se_select_dma_mode(void __iomem *base)		static int geni_se_select_dma_mode(void __iomem *base)
	{		{
	int proto = get_se_proto(base);
	unsigned int geni_dma_mode = 0;		unsigned int geni_dma_mode = 0;
	unsigned int common_geni_m_irq_en;

	geni_write_reg(0, base, SE_GSI_EVENT_EN);		geni_write_reg(0, base, SE_GSI_EVENT_EN);
	geni_write_reg(0xFFFFFFFF, base, SE_GENI_M_IRQ_CLEAR);		geni_write_reg(0xFFFFFFFF, base, SE_GENI_M_IRQ_CLEAR);
	@@ -319,13 +321,9 @@ static int geni_se_select_dma_mode(void __iomem *base)
	geni_write_reg(0xFFFFFFFF, base, SE_DMA_TX_IRQ_CLR);		geni_write_reg(0xFFFFFFFF, base, SE_DMA_TX_IRQ_CLR);
	geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR);		geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR);
	geni_write_reg(0xFFFFFFFF, base, SE_IRQ_EN);		geni_write_reg(0xFFFFFFFF, base, SE_IRQ_EN);
			geni_write_reg(0x00000000, base, SE_GENI_M_IRQ_EN);
			geni_write_reg(0x00000000, base, SE_GENI_S_IRQ_EN);

	common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN);
	if (proto != UART)
	common_geni_m_irq_en &=
	~(M_TX_FIFO_WATERMARK_EN \| M_RX_FIFO_WATERMARK_EN);

	geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN);
	geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN);		geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN);
	geni_dma_mode \|= GENI_DMA_MODE_EN;		geni_dma_mode \|= GENI_DMA_MODE_EN;
	geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN);		geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN);