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Commit b3843414 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Sekhar Nori
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ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x 



McASP1 TX interrupt is 30, not 32 on DM646x DMSoC.

While at it remove the bogus AEMIF interrupt entry from
dm646x_default_priorities[]. AEMIF interrupt on DM6467 is
60 not 30 and the entry for the correct interrupt number
is already present in the same table.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: remove bogus entry from dm646x_default_priorities[]]
Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
parent 256b20a5

arch/arm/mach-davinci/dm646x.c

+0 −1
Original line number Diff line number Diff line
@@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { 
	[IRQ_DM646X_EMACMISCINT]        = 7,

	[IRQ_DM646X_MCASP0TXINT]        = 7,

	[IRQ_DM646X_MCASP0RXINT]        = 7,

	[IRQ_AEMIFINT]                  = 7,

	[IRQ_DM646X_RESERVED_3]         = 7,

	[IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */

	[IRQ_TINT0_TINT34]              = 7,    /* clocksource */

arch/arm/mach-davinci/include/mach/irqs.h

+1 −1
Original line number Diff line number Diff line
@@ -129,8 +129,8 @@ 
#define IRQ_DM646X_EMACMISCINT  27

#define IRQ_DM646X_MCASP0TXINT  28

#define IRQ_DM646X_MCASP0RXINT  29

#define IRQ_DM646X_MCASP1TXINT  30

#define IRQ_DM646X_RESERVED_3   31

#define IRQ_DM646X_MCASP1TXINT  32

#define IRQ_DM646X_VLQINT       38

#define IRQ_DM646X_UARTINT2     42

#define IRQ_DM646X_SPINT0       43