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Commit b36f7d26 authored by Dave Airlie's avatar Dave Airlie Committed by Alex Deucher
Browse files

drm/radeon/mst: fix regression in lane/link handling. 



The function this used changed in
    092c96a8
    drm/radeon: fix dp link rate selection (v2)

However for MST we should just always train to the
max link/rate. Though we probably need to limit this
for future hw, in theory radeon won't support it.

This fixes my 30" monitor with MST enabled.

Cc: stable@vger.kernel.org # v4.4
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ae20f12d

drivers/gpu/drm/radeon/radeon_dp_mst.c

+2 −10
Original line number Diff line number Diff line
@@ -525,17 +525,9 @@ static bool radeon_mst_mode_fixup(struct drm_encoder *encoder, 
	drm_mode_set_crtcinfo(adjusted_mode, 0);

	{

	  struct radeon_connector_atom_dig *dig_connector;

	  int ret;



	  dig_connector = mst_enc->connector->con_priv;

	  ret = radeon_dp_get_dp_link_config(&mst_enc->connector->base,

					     dig_connector->dpcd, adjusted_mode->clock,

					     &dig_connector->dp_lane_count,

					     &dig_connector->dp_clock);

	  if (ret) {

		  dig_connector->dp_lane_count = 0;

		  dig_connector->dp_clock = 0;

	  }

	  dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);

	  dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);

	  DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,

			dig_connector->dp_lane_count, dig_connector->dp_clock);

	}