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Commit b369ebf6 authored by Anaadi Mishra's avatar Anaadi Mishra
Browse files

clk: qcom: gcc-scuba: Add gcc_pwm0_xo512_div_clk_src clk support 



Add gcc_pwm0_xo512_div_clk_src as parent of gcc_pwm0_xo512_clk
to support the pdm_pwm functionality.

Change-Id: Ida37f2a833881640c1d31d6d723ecbe715b701a0
Signed-off-by: default avatarAnaadi Mishra <quic_anaadim@quicinc.com>
parent 6dd29f8f

drivers/clk/qcom/gcc-scuba.c

+19 −0
Original line number Diff line number Diff line
@@ -2246,6 +2246,19 @@ static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 
	},

};



static struct clk_regmap_div gcc_pwm0_xo512_div_clk_src = {

	.reg = 0x20030,

	.shift = 0,

	.width = 9,

	.clkr.hw.init = &(const struct clk_init_data) {

		.name = "gcc_pwm0_xo512_div_clk_src",

		.parent_names =

			(const char *[]){ "bi_tcxo" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ops,

	},

};



static struct clk_branch gcc_disp_gpll0_div_clk_src = {

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {
@@ -2522,6 +2535,11 @@ static struct clk_branch gcc_pwm0_xo512_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pwm0_xo512_clk",

			.parent_names = (const char *[]){

				"gcc_pwm0_xo512_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3178,6 +3196,7 @@ static struct clk_regmap *gcc_scuba_clocks[] = { 
	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,

	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,

	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,

	[GCC_PWM0_XO512_DIV_CLK_SRC] = &gcc_pwm0_xo512_div_clk_src.clkr,

	[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,

	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,

	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,