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Commit b31e85ed authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: Detect USB-C specific dongles before reducing M and N 

The Analogix 7737 DP to HDMI converter requires reduced M and N values
when to operate correctly at HBR2. We tried to reduce the M/N values for
all devices in commit 9a86cda0 ("drm/i915/dp: reduce link M/N
parameters"), but that regressed some other sinks. Detect this IC by its
OUI value of 0x0022B9 via the DPCD quirk list, and only reduce the M/N
values for that.

v2 by Jani: Rebased on the DP quirk database

v3 by Jani: Rebased on the reworked DP quirk database

v4 by Jani: Improve commit message (Daniel)

Fixes: 9a86cda0 ("drm/i915/dp: reduce link M/N parameters")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93578
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100755


Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarClint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/2d2e30f8f47d3f28c9b74ca2612336a54585c3ec.1495105635.git.jani.nikula@intel.com
parent 76fa998a

drivers/gpu/drm/i915/i915_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -562,7 +562,8 @@ struct intel_link_m_n { 


void intel_link_compute_m_n(int bpp, int nlanes,

			    int pixel_clock, int link_clock,

			    struct intel_link_m_n *m_n);

			    struct intel_link_m_n *m_n,

			    bool reduce_m_n);



/* Interface history:

 *

drivers/gpu/drm/i915/intel_display.c

+14 −8
Original line number Diff line number Diff line
@@ -6101,7 +6101,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, 
	pipe_config->fdi_lanes = lane;



	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,

			       link_bw, &pipe_config->fdi_m_n);

			       link_bw, &pipe_config->fdi_m_n, false);



	ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);

	if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
@@ -6277,7 +6277,8 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) 
}



static void compute_m_n(unsigned int m, unsigned int n,

			uint32_t *ret_m, uint32_t *ret_n)

			uint32_t *ret_m, uint32_t *ret_n,

			bool reduce_m_n)

{

	/*

	 * Reduce M/N as much as possible without loss in precision. Several DP
@@ -6285,10 +6286,12 @@ static void compute_m_n(unsigned int m, unsigned int n, 
	 * values. The passed in values are more likely to have the least

	 * significant bits zero than M after rounding below, so do this first.

	 */

	if (reduce_m_n) {

		while ((m & 1) == 0 && (n & 1) == 0) {

			m >>= 1;

			n >>= 1;

		}

	}



	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);

	*ret_m = div_u64((uint64_t) m * *ret_n, n);
@@ -6298,16 +6301,19 @@ static void compute_m_n(unsigned int m, unsigned int n, 
void

intel_link_compute_m_n(int bits_per_pixel, int nlanes,

		       int pixel_clock, int link_clock,

		       struct intel_link_m_n *m_n)

		       struct intel_link_m_n *m_n,

		       bool reduce_m_n)

{

	m_n->tu = 64;



	compute_m_n(bits_per_pixel * pixel_clock,

		    link_clock * nlanes * 8,

		    &m_n->gmch_m, &m_n->gmch_n);

		    &m_n->gmch_m, &m_n->gmch_n,

		    reduce_m_n);



	compute_m_n(pixel_clock, link_clock,

		    &m_n->link_m, &m_n->link_n);

		    &m_n->link_m, &m_n->link_n,

		    reduce_m_n);

}



static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_dp.c

+6 −2
Original line number Diff line number Diff line
@@ -1593,6 +1593,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
	int common_rates[DP_MAX_SUPPORTED_RATES] = {};

	int common_len;

	uint8_t link_bw, rate_select;

	bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,

					   DP_DPCD_QUIRK_LIMITED_M_N);



	common_len = intel_dp_common_rates(intel_dp, common_rates);
@@ -1722,7 +1724,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
	intel_link_compute_m_n(bpp, lane_count,

			       adjusted_mode->crtc_clock,

			       pipe_config->port_clock,

			       &pipe_config->dp_m_n);

			       &pipe_config->dp_m_n,

			       reduce_m_n);



	if (intel_connector->panel.downclock_mode != NULL &&

		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
@@ -1730,7 +1733,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
			intel_link_compute_m_n(bpp, lane_count,

				intel_connector->panel.downclock_mode->clock,

				pipe_config->port_clock,

				&pipe_config->dp_m2_n2);

				&pipe_config->dp_m2_n2,

				reduce_m_n);

	}



	/*

drivers/gpu/drm/i915/intel_dp_mst.c

+4 −1
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, 
	int lane_count, slots;

	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;

	int mst_pbn;

	bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,

					   DP_DPCD_QUIRK_LIMITED_M_N);



	pipe_config->has_pch_encoder = false;

	bpp = 24;
@@ -75,7 +77,8 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, 
	intel_link_compute_m_n(bpp, lane_count,

			       adjusted_mode->crtc_clock,

			       pipe_config->port_clock,

			       &pipe_config->dp_m_n);

			       &pipe_config->dp_m_n,

			       reduce_m_n);



	pipe_config->dp_m_n.tu = slots;