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Commit b30fdd6f authored by Steven J. Hill's avatar Steven J. Hill Committed by Ralf Baechle
Browse files

MIPS: MIPSsim: Remove the MIPSsim platform. 



The MIPSsim platform is no longer supported or used.

[ralf@linux-mips.org: Also remove mipssim from arch/mips/Kbuild.platforms
and delete arch/mips/include/asm/mach-mipssim/*.]

Signed-off-by: default avatarSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4350/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b1c56184

arch/mips/Kbuild.platforms

+0 −1
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ platforms += lantiq 
platforms += lasat

platforms += loongson

platforms += loongson1

platforms += mipssim

platforms += mti-malta

platforms += netlogic

platforms += pmc-sierra

arch/mips/Kconfig

+0 −19
Original line number Diff line number Diff line
@@ -319,25 +319,6 @@ config MIPS_MALTA 
	  This enables support for the MIPS Technologies Malta evaluation

	  board.



config MIPS_SIM

	bool 'MIPS simulator (MIPSsim)'

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK

	select IRQ_CPU

	select BOOT_RAW

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_HAS_EARLY_PRINTK

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_MULTITHREADING

	select SYS_SUPPORTS_LITTLE_ENDIAN

	help

	  This option enables support for MIPS Technologies MIPSsim software

	  emulator.



config NEC_MARKEINS

	bool "NEC EMMA2RH Mark-eins board"

	select SOC_EMMA2RH

arch/mips/configs/mipssim_defconfig

deleted100644 → 0
+0 −64
Original line number Diff line number Diff line 
CONFIG_MIPS_SIM=y

CONFIG_CPU_LITTLE_ENDIAN=y

CONFIG_HZ_100=y

# CONFIG_SECCOMP is not set

CONFIG_EXPERIMENTAL=y

# CONFIG_SWAP is not set

CONFIG_SYSVIPC=y

CONFIG_LOG_BUF_SHIFT=14

# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set

CONFIG_EXPERT=y

CONFIG_SLAB=y

CONFIG_MODULES=y

CONFIG_MODULE_UNLOAD=y

CONFIG_MODVERSIONS=y

CONFIG_MODULE_SRCVERSION_ALL=y

# CONFIG_BLK_DEV_BSG is not set

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_UNIX=y

CONFIG_INET=y

CONFIG_IP_MULTICAST=y

CONFIG_IP_ADVANCED_ROUTER=y

CONFIG_IP_PNP=y

CONFIG_IP_PNP_DHCP=y

CONFIG_IP_PNP_BOOTP=y

# CONFIG_INET_XFRM_MODE_TRANSPORT is not set

# CONFIG_INET_XFRM_MODE_TUNNEL is not set

# CONFIG_INET_XFRM_MODE_BEET is not set

# CONFIG_INET_LRO is not set

# CONFIG_IPV6 is not set

CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"

# CONFIG_STANDALONE is not set

# CONFIG_PREVENT_FIRMWARE_BUILD is not set

# CONFIG_FW_LOADER is not set

CONFIG_BLK_DEV_LOOP=y

CONFIG_BLK_DEV_NBD=y

# CONFIG_MISC_DEVICES is not set

CONFIG_NETDEVICES=y

CONFIG_NET_ETHERNET=y

CONFIG_MIPS_SIM_NET=y

# CONFIG_NETDEV_1000 is not set

# CONFIG_NETDEV_10000 is not set

# CONFIG_INPUT is not set

# CONFIG_SERIO is not set

# CONFIG_VT is not set

CONFIG_SERIAL_8250=y

CONFIG_SERIAL_8250_CONSOLE=y

CONFIG_SERIAL_8250_NR_UARTS=1

CONFIG_SERIAL_8250_RUNTIME_UARTS=1

# CONFIG_HW_RANDOM is not set

# CONFIG_HWMON is not set

# CONFIG_USB_SUPPORT is not set

# CONFIG_DNOTIFY is not set

CONFIG_TMPFS=y

CONFIG_ROMFS_FS=y

CONFIG_NFS_FS=y

CONFIG_NFS_V3=y

CONFIG_ROOT_NFS=y

CONFIG_DEBUG_KERNEL=y

# CONFIG_SCHED_DEBUG is not set

CONFIG_DEBUG_INFO=y

CONFIG_CMDLINE_BOOL=y

CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"

# CONFIG_CRC32 is not set

arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h

deleted100644 → 0
+0 −67
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2003, 2004 Chris Dearman

 */

#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H

#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H





/*

 * CPU feature overrides for MIPS boards

 */

#ifdef CONFIG_CPU_MIPS32

#define cpu_has_tlb		1

#define cpu_has_4kex		1

#define cpu_has_4k_cache	1

#define cpu_has_fpu		0

/* #define cpu_has_32fpr	? */

#define cpu_has_counter		1

/* #define cpu_has_watch	? */

#define cpu_has_divec		1

#define cpu_has_vce		0

/* #define cpu_has_cache_cdex_p	? */

/* #define cpu_has_cache_cdex_s	? */

/* #define cpu_has_prefetch	? */

#define cpu_has_mcheck		1

/* #define cpu_has_ejtag	? */

#define cpu_has_llsc		1

/* #define cpu_has_vtag_icache	? */

/* #define cpu_has_dc_aliases	? */

/* #define cpu_has_ic_fills_f_dc ? */

#define cpu_has_clo_clz		1

#define cpu_has_nofpuex		0

/* #define cpu_has_64bits	? */

/* #define cpu_has_64bit_zero_reg ? */

/* #define cpu_has_inclusive_pcaches ? */

#endif



#ifdef CONFIG_CPU_MIPS64

#define cpu_has_tlb		1

#define cpu_has_4kex		1

#define cpu_has_4k_cache	1

/* #define cpu_has_fpu		? */

/* #define cpu_has_32fpr	? */

#define cpu_has_counter		1

/* #define cpu_has_watch	? */

#define cpu_has_divec		1

#define cpu_has_vce		0

/* #define cpu_has_cache_cdex_p	? */

/* #define cpu_has_cache_cdex_s	? */

/* #define cpu_has_prefetch	? */

#define cpu_has_mcheck		1

/* #define cpu_has_ejtag	? */

#define cpu_has_llsc		1

/* #define cpu_has_vtag_icache	? */

/* #define cpu_has_dc_aliases	? */

/* #define cpu_has_ic_fills_f_dc ? */

#define cpu_has_clo_clz		1

#define cpu_has_nofpuex		0

/* #define cpu_has_64bits	? */

/* #define cpu_has_64bit_zero_reg ? */

/* #define cpu_has_inclusive_pcaches ? */

#endif



#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */

arch/mips/include/asm/mach-mipssim/war.h

deleted100644 → 0
+0 −25
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>

 */

#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H

#define __ASM_MIPS_MACH_MIPSSIM_WAR_H



#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

#define MIPS_CACHE_SYNC_WAR		0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define RM9000_CDEX_SMP_WAR		0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0



#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */