Merge "msm: camera: cpas: Add support to GPU limit" into camera-kernel.lnx.3.1 (b2da4b68) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/cam_cpas/cam_cpas_hw.c

+26 −1

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2017-2020 The Linux Foundation. All rights reserved.
		*/

		#include <linux/device.h>
		@@ -1174,6 +1174,23 @@ static int cam_cpas_hw_start(void hw_priv, void start_args,
		if (rc)
		goto done;

		if ((soc_private->cx_ipeak_gpu_limit) &&
		(!cpas_core->streamon_clients)) {
		soc_private->gpu_pwr_limit =
		kgsl_pwr_limits_add(KGSL_DEVICE_3D0);
		if (soc_private->gpu_pwr_limit) {
		rc = kgsl_pwr_limits_set_freq(
		soc_private->gpu_pwr_limit,
		soc_private->cx_ipeak_gpu_limit);
		if (rc) {
		kgsl_pwr_limits_del(
		soc_private->gpu_pwr_limit);
		soc_private->gpu_pwr_limit = NULL;
		goto done;
		}
		}
		}

		if (cpas_core->streamon_clients == 0) {
		atomic_set(&cpas_core->irq_count, 1);
		rc = cam_cpas_soc_enable_resources(&cpas_hw->soc_info,
		@@ -1308,6 +1325,14 @@ static int cam_cpas_hw_stop(void hw_priv, void stop_args,
		CAM_DBG(CAM_CPAS, "Disabled all the resources: irq_count=%d\n",
		atomic_read(&cpas_core->irq_count));
		cpas_hw->hw_state = CAM_HW_STATE_POWER_DOWN;

		if (soc_private->cx_ipeak_gpu_limit &&
		soc_private->gpu_pwr_limit) {
		kgsl_pwr_limits_set_default(
		soc_private->gpu_pwr_limit);
		kgsl_pwr_limits_del(soc_private->gpu_pwr_limit);
		soc_private->gpu_pwr_limit = NULL;
		}
		}

		ahb_vote.type = CAM_VOTE_ABSOLUTE;

+4 −1

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2017-2020 The Linux Foundation. All rights reserved.
		*/

		#include <linux/device.h>
		@@ -553,6 +553,9 @@ int cam_cpas_get_custom_dt_info(struct cam_hw_info *cpas_hw,
		goto cleanup_tree;
		}

		of_property_read_u32(of_node, "qcom,cx-ipeak-gpu-limit",
		&soc_private->cx_ipeak_gpu_limit);

		return 0;

		cleanup_tree:

+6 −1

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2017-2020 The Linux Foundation. All rights reserved.
		*/

		#ifndef _CAM_CPAS_SOC_H_
		#define _CAM_CPAS_SOC_H_

		#include <linux/msm_kgsl.h>
		#include "cam_soc_util.h"
		#include "cam_cpas_hw.h"

		@@ -88,6 +89,8 @@ struct cam_cpas_tree_node {
		* camnoc axi clock
		* @camnoc_axi_min_ib_bw: Min camnoc BW which varies based on target
		* @feature_mask: feature mask value for hw supported features
		* @cx_ipeak_gpu_limit: Flag for Cx Ipeak GPU mitigation
		* @gpu_pwr_limit: Handle for Cx Ipeak GPU Mitigation
		*
		*/
		struct cam_cpas_private_soc {
		@@ -105,6 +108,8 @@ struct cam_cpas_private_soc {
		uint32_t camnoc_axi_clk_bw_margin;
		uint64_t camnoc_axi_min_ib_bw;
		uint32_t feature_mask;
		uint32_t cx_ipeak_gpu_limit;
		struct kgsl_pwr_limit *gpu_pwr_limit;
		};

		void cam_cpas_util_debug_parse_data(struct cam_cpas_private_soc *soc_private);