Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b284fbe3 authored by Nobuhiro Iwamatsu's avatar Nobuhiro Iwamatsu Committed by David S. Miller
Browse files

sh_eth: Fix access to TRSCER register 



TRSCER register is configured differently by SoCs. TRSCER of R-Car Gen2 is
RINT8 bit only valid, other bits are reserved bits. This removes access to
TRSCER register reserve bit by adding variable trscer_err_mask to
sh_eth_cpu_data structure, set the register information to each SoCs.

Signed-off-by: default avatarNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d407bc02

drivers/net/ethernet/renesas/sh_eth.c

+6 −1
Original line number Diff line number Diff line
@@ -538,6 +538,8 @@ static struct sh_eth_cpu_data sh7724_data = { 
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |

			  EESR_ECI,



	.trscer_err_mask = DESC_I_RINT8,



	.apr		= 1,

	.mpr		= 1,

	.tpauser	= 1,
@@ -858,6 +860,9 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 


	if (!cd->eesr_err_check)

		cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;



	if (!cd->trscer_err_mask)

		cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;

}



static int sh_eth_check_reset(struct net_device *ndev)
@@ -1296,7 +1301,7 @@ static int sh_eth_dev_init(struct net_device *ndev, bool start) 
	/* Frame recv control (enable multiple-packets per rx irq) */

	sh_eth_write(ndev, RMCR_RNC, RMCR);



	sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);

	sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);



	if (mdp->cd->bculr)

		sh_eth_write(ndev, 0x800, BCULR);	/* Burst sycle set */

drivers/net/ethernet/renesas/sh_eth.h

+5 −0
Original line number Diff line number Diff line
@@ -369,6 +369,8 @@ enum DESC_I_BIT { 
	DESC_I_RINT1 = 0x0001,

};



#define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2)



/* RPADIR */

enum RPADIR_BIT {

	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
@@ -470,6 +472,9 @@ struct sh_eth_cpu_data { 
	unsigned long tx_check;

	unsigned long eesr_err_check;



	/* Error mask */

	unsigned long trscer_err_mask;



	/* hardware features */

	unsigned long irq_flags; /* IRQ configuration flags */

	unsigned no_psr:1;	/* EtherC DO NOT have PSR */