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Commit b26cd30c authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux into next/dt 

From Maxime Ripard <maxime.ripard@free-electrons.com>:

ARM: sunxi: dt additions for 3.10, take 2

  - Rename the clock compatible introduced in the first pull request for 3.10
  - Complete the UART support for A13 and A10
  - Adds clock gates support

* tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux

:
  arm: sunxi: Add clock to pinctrl node
  arm: sunxi: use the right clock phandles for UARTs
  arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
  ARM: sunxi: cubieboard: Add UART muxing
  ARM: sunxi: hackberry: Add UART muxing
  ARM: sunxi: dt: Add A10 UARTs to the dtsi.
  ARM: sunxi: dt: Add uart3 dt node
  ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi
  ARM: sunxi: Rename uart nodes to serial
  ARM: sunxi: dt: Use clocks property instead of clock-frequency for the UARTs
  arm: sunxi: rename clock compatible strings

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents e52ec428 36386d6e

arch/arm/boot/dts/sun4i-a10-cubieboard.dts

+3 −5
Original line number Diff line number Diff line
@@ -36,11 +36,9 @@ 
			};

		};



		uart0: uart@01c28000 {

			status = "okay";

		};



		uart1: uart@01c28400 {

		uart0: serial@01c28000 {

			pinctrl-names = "default";

			pinctrl-0 = <&uart0_pins_a>;

			status = "okay";

		};

	};

arch/arm/boot/dts/sun4i-a10-hackberry.dts

+3 −1
Original line number Diff line number Diff line
@@ -23,7 +23,9 @@ 
	};



	soc {

		uart0: uart@01c28000 {

		uart0: serial@01c28000 {

			pinctrl-names = "default";

			pinctrl-0 = <&uart0_pins_a>;

			status = "okay";

		};

	};

arch/arm/boot/dts/sun4i-a10.dtsi

+61 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
		pio: pinctrl@01c20800 {

			compatible = "allwinner,sun4i-a10-pinctrl";

			reg = <0x01c20800 0x400>;

			clocks = <&apb0_gates 5>;

			gpio-controller;

			#address-cells = <1>;

			#size-cells = <0>;
@@ -47,5 +48,65 @@ 
				allwinner,pull = <0>;

			};

		};



		uart0: serial@01c28000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28000 0x400>;

			interrupts = <1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 16>;

			status = "disabled";

		};



		uart2: serial@01c28800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28800 0x400>;

			interrupts = <3>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 18>;

			status = "disabled";

		};



		uart4: serial@01c29000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29000 0x400>;

			interrupts = <17>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 20>;

			status = "disabled";

		};



		uart5: serial@01c29400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29400 0x400>;

			interrupts = <18>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 21>;

			status = "disabled";

		};



		uart6: serial@01c29800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29800 0x400>;

			interrupts = <19>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 22>;

			status = "disabled";

		};



		uart7: serial@01c29c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29c00 0x400>;

			interrupts = <20>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 23>;

			status = "disabled";

		};

	};

};

arch/arm/boot/dts/sun5i-a13-olinuxino.dts

+1 −1
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
			};

		};



		uart1: uart@01c28400 {

		uart1: serial@01c28400 {

			pinctrl-names = "default";

			pinctrl-0 = <&uart1_pins_b>;

			status = "okay";

arch/arm/boot/dts/sun5i-a13.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
		pio: pinctrl@01c20800 {

			compatible = "allwinner,sun5i-a13-pinctrl";

			reg = <0x01c20800 0x400>;

			clocks = <&apb0_gates 5>;

			gpio-controller;

			#address-cells = <1>;

			#size-cells = <0>;