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Commit b246f1ea authored by Yue Ma's avatar Yue Ma
Browse files

cnss2: Config MHI M2 timeout value



The timeout is used to wait for MHI entering M2 state from M0 state.
Make the timeout dynamically configurable as well.

Change-Id: If7be79226e8428bb8880d86a79a7cac14f656f19
Signed-off-by: default avatarYue Ma <yuem@codeaurora.org>
parent efb42990
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+4 −0
Original line number Diff line number Diff line
@@ -557,6 +557,8 @@ static ssize_t cnss_control_params_debug_write(struct file *fp,
		plat_priv->ctrl_params.quirks = val;
	else if (strcmp(cmd, "mhi_timeout") == 0)
		plat_priv->ctrl_params.mhi_timeout = val;
	else if (strcmp(cmd, "mhi_m2_timeout") == 0)
		plat_priv->ctrl_params.mhi_m2_timeout = val;
	else if (strcmp(cmd, "qmi_timeout") == 0)
		plat_priv->ctrl_params.qmi_timeout = val;
	else if (strcmp(cmd, "bdf_type") == 0)
@@ -638,6 +640,8 @@ static int cnss_control_params_debug_show(struct seq_file *s, void *data)
	seq_puts(s, "\nCurrent value:\n");
	cnss_show_quirks_state(s, cnss_priv);
	seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout);
	seq_printf(s, "mhi_m2_timeout: %u\n",
		   cnss_priv->ctrl_params.mhi_m2_timeout);
	seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout);
	seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type);
	seq_printf(s, "time_sync_period: %u\n",
+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@
#else
#define CNSS_MHI_TIMEOUT_DEFAULT	0
#endif
#define CNSS_MHI_M2_TIMEOUT_DEFAULT	25
#define CNSS_QMI_TIMEOUT_DEFAULT	10000
#define CNSS_BDF_TYPE_DEFAULT		CNSS_BDF_ELF
#define CNSS_TIME_SYNC_PERIOD_DEFAULT	900000
@@ -1911,6 +1912,7 @@ static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
{
	plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
	plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
	plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
	plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
	plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
	plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
+1 −0
Original line number Diff line number Diff line
@@ -260,6 +260,7 @@ struct cnss_cal_info {
struct cnss_control_params {
	unsigned long quirks;
	unsigned int mhi_timeout;
	unsigned int mhi_m2_timeout;
	unsigned int qmi_timeout;
	unsigned int bdf_type;
	unsigned int time_sync_period;
+2 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ static DEFINE_SPINLOCK(pci_link_down_lock);
static DEFINE_SPINLOCK(pci_reg_window_lock);

#define MHI_TIMEOUT_OVERWRITE_MS	(plat_priv->ctrl_params.mhi_timeout)
#define MHI_M2_TIMEOUT_MS		(plat_priv->ctrl_params.mhi_m2_timeout)

#define FORCE_WAKE_DELAY_MIN_US			4000
#define FORCE_WAKE_DELAY_MAX_US			6000
@@ -937,6 +938,7 @@ int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv)

	if (MHI_TIMEOUT_OVERWRITE_MS)
		pci_priv->mhi_ctrl->timeout_ms = MHI_TIMEOUT_OVERWRITE_MS;
	pci_priv->mhi_ctrl->m2_timeout_ms = MHI_M2_TIMEOUT_MS;

	ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_INIT);
	if (ret)