Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b244ffa1 authored by Zhenyu Wang's avatar Zhenyu Wang
Browse files

drm/i915/gvt: Fix drm_format_mod value for vGPU plane 



Physical plane's tiling mode value is given directly as
drm_format_mod for plane query, which is not correct fourcc
code. Fix it by using correct intel tiling fourcc mod definition.

Current qemu seems also doesn't correctly utilize drm_format_mod
for plane object setting. Anyway this is required to fix the usage.

v3: use DRM_FORMAT_MOD_LINEAR, fix comment

v2: Fix missed old 'tiled' use for stride calculation

Fixes: e546e281 ("drm/i915/gvt: Dmabuf support for GVT-g")
Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Colin Xu <Colin.Xu@intel.com>
Reviewed-by: default avatarColin Xu <Colin.Xu@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent b2b599fb

drivers/gpu/drm/i915/gvt/dmabuf.c

+26 −7
Original line number Diff line number Diff line
@@ -170,20 +170,22 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, 
		unsigned int tiling_mode = 0;

		unsigned int stride = 0;



		switch (info->drm_format_mod << 10) {

		case PLANE_CTL_TILED_LINEAR:

		switch (info->drm_format_mod) {

		case DRM_FORMAT_MOD_LINEAR:

			tiling_mode = I915_TILING_NONE;

			break;

		case PLANE_CTL_TILED_X:

		case I915_FORMAT_MOD_X_TILED:

			tiling_mode = I915_TILING_X;

			stride = info->stride;

			break;

		case PLANE_CTL_TILED_Y:

		case I915_FORMAT_MOD_Y_TILED:

		case I915_FORMAT_MOD_Yf_TILED:

			tiling_mode = I915_TILING_Y;

			stride = info->stride;

			break;

		default:

			gvt_dbg_core("not supported tiling mode\n");

			gvt_dbg_core("invalid drm_format_mod %llx for tiling\n",

				     info->drm_format_mod);

		}

		obj->tiling_and_stride = tiling_mode | stride;

	} else {
@@ -222,7 +224,24 @@ static int vgpu_get_plane_info(struct drm_device *dev, 
		info->height = p.height;

		info->stride = p.stride;

		info->drm_format = p.drm_format;

		info->drm_format_mod = p.tiled;



		switch (p.tiled) {

		case PLANE_CTL_TILED_LINEAR:

			info->drm_format_mod = DRM_FORMAT_MOD_LINEAR;

			break;

		case PLANE_CTL_TILED_X:

			info->drm_format_mod = I915_FORMAT_MOD_X_TILED;

			break;

		case PLANE_CTL_TILED_Y:

			info->drm_format_mod = I915_FORMAT_MOD_Y_TILED;

			break;

		case PLANE_CTL_TILED_YF:

			info->drm_format_mod = I915_FORMAT_MOD_Yf_TILED;

			break;

		default:

			gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled);

		}



		info->size = (((p.stride * p.height * p.bpp) / 8) +

			      (PAGE_SIZE - 1)) >> PAGE_SHIFT;

	} else if (plane_id == DRM_PLANE_TYPE_CURSOR) {

drivers/gpu/drm/i915/gvt/fb_decoder.c

+2 −3
Original line number Diff line number Diff line
@@ -220,8 +220,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 
	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

		plane->tiled = (val & PLANE_CTL_TILED_MASK) >>

		_PLANE_CTL_TILED_SHIFT;

		plane->tiled = val & PLANE_CTL_TILED_MASK;

		fmt = skl_format_to_drm(

			val & PLANE_CTL_FORMAT_MASK,

			val & PLANE_CTL_ORDER_RGBX,
@@ -260,7 +259,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 
		return  -EINVAL;

	}



	plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),

	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,

		(IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) ?

drivers/gpu/drm/i915/gvt/fb_decoder.h

+1 −1
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ struct intel_gvt; 
/* color space conversion and gamma correction are not included */

struct intel_vgpu_primary_plane_format {

	u8	enabled;	/* plane is enabled */

	u8	tiled;		/* X-tiled */

	u32	tiled;		/* tiling mode: linear, X-tiled, Y tiled, etc */

	u8	bpp;		/* bits per pixel */

	u32	hw_format;	/* format field in the PRI_CTL register */

	u32	drm_format;	/* format in DRM definition */