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Commit b22267d3 authored by Krzysztof Hałasa's avatar Krzysztof Hałasa
Browse files

WAN: Convert PC300 driver to use normal u8/u16/u32 types 



Signed-off-by: default avatarKrzysztof Hałasa <khc@pm.waw.pl>
parent c36936ce

drivers/net/wan/pc300.h

+90 −94
Original line number Diff line number Diff line
@@ -103,10 +103,6 @@ 
#include "hd64572.h"

#include "pc300-falc-lh.h"



typedef	__u32	uclong;		/* 32 bits, unsigned */

typedef	__u16	ucshort;	/* 16 bits, unsigned */

typedef	__u8	ucchar;		/* 8 bits, unsigned */



#define PC300_PROTO_MLPPP 1



#define	PC300_MAXCHAN	2	/* Number of channels per card */
@@ -147,9 +143,9 @@ typedef __u8 ucchar; /* 8 bits, unsigned */ 
 * Memory access functions/macros      *

 * (required to support Alpha systems) *

 ***************************************/

#define cpc_writeb(port,val)	{writeb((ucchar)(val),(port)); mb();}

#define cpc_writeb(port,val)	{writeb((u8)(val),(port)); mb();}

#define cpc_writew(port,val)	{writew((ushort)(val),(port)); mb();}

#define cpc_writel(port,val)	{writel((uclong)(val),(port)); mb();}

#define cpc_writel(port,val)	{writel((u32)(val),(port)); mb();}



#define cpc_readb(port)		readb(port)

#define cpc_readw(port)		readw(port)
@@ -163,15 +159,15 @@ typedef __u8 ucchar; /* 8 bits, unsigned */ 
 *      (memory mapped).

 */

struct RUNTIME_9050 {

	uclong	loc_addr_range[4];	/* 00-0Ch : Local Address Ranges */

	uclong	loc_rom_range;		/* 10h : Local ROM Range */

	uclong	loc_addr_base[4];	/* 14-20h : Local Address Base Addrs */

	uclong	loc_rom_base;		/* 24h : Local ROM Base */

	uclong	loc_bus_descr[4];	/* 28-34h : Local Bus Descriptors */

	uclong	rom_bus_descr;		/* 38h : ROM Bus Descriptor */

	uclong	cs_base[4];		/* 3C-48h : Chip Select Base Addrs */

	uclong	intr_ctrl_stat;		/* 4Ch : Interrupt Control/Status */

	uclong	init_ctrl;		/* 50h : EEPROM ctrl, Init Ctrl, etc */

	u32 loc_addr_range[4];	/* 00-0Ch : Local Address Ranges */

	u32 loc_rom_range;	/* 10h : Local ROM Range */

	u32 loc_addr_base[4];	/* 14-20h : Local Address Base Addrs */

	u32 loc_rom_base;	/* 24h : Local ROM Base */

	u32 loc_bus_descr[4];	/* 28-34h : Local Bus Descriptors */

	u32 rom_bus_descr;	/* 38h : ROM Bus Descriptor */

	u32 cs_base[4];		/* 3C-48h : Chip Select Base Addrs */

	u32 intr_ctrl_stat;	/* 4Ch : Interrupt Control/Status */

	u32 init_ctrl;		/* 50h : EEPROM ctrl, Init Ctrl, etc */

};



#define PLX_9050_LINT1_ENABLE	0x01
@@ -215,66 +211,66 @@ struct RUNTIME_9050 { 
#define PC300_FALC_MAXLOOP	0x0000ffff	/* for falc_issue_cmd() */



typedef struct falc {

	ucchar sync;		/* If true FALC is synchronized */

	ucchar active;		/* if TRUE then already active */

	ucchar loop_active;	/* if TRUE a line loopback UP was received */

	ucchar loop_gen;	/* if TRUE a line loopback UP was issued */

	u8 sync;	/* If true FALC is synchronized */

	u8 active;	/* if TRUE then already active */

	u8 loop_active;	/* if TRUE a line loopback UP was received */

	u8 loop_gen;	/* if TRUE a line loopback UP was issued */



	ucchar num_channels;

	ucchar offset;		/* 1 for T1, 0 for E1 */

	ucchar full_bandwidth;

	u8 num_channels;

	u8 offset;	/* 1 for T1, 0 for E1 */

	u8 full_bandwidth;



	ucchar xmb_cause;

	ucchar multiframe_mode;

	u8 xmb_cause;

	u8 multiframe_mode;



	/* Statistics */

	ucshort pden;	/* Pulse Density violation count */

	ucshort los;	/* Loss of Signal count */

	ucshort losr;	/* Loss of Signal recovery count */

	ucshort lfa;	/* Loss of frame alignment count */

	ucshort farec;	/* Frame Alignment Recovery count */

	ucshort lmfa;	/* Loss of multiframe alignment count */

	ucshort ais;	/* Remote Alarm indication Signal count */

	ucshort sec;	/* One-second timer */

	ucshort es;	/* Errored second */

	ucshort rai;	/* remote alarm received */

	ucshort bec;

	ucshort fec;

	ucshort cvc;

	ucshort cec;

	ucshort ebc;

	u16 pden;	/* Pulse Density violation count */

	u16 los;	/* Loss of Signal count */

	u16 losr;	/* Loss of Signal recovery count */

	u16 lfa;	/* Loss of frame alignment count */

	u16 farec;	/* Frame Alignment Recovery count */

	u16 lmfa;	/* Loss of multiframe alignment count */

	u16 ais;	/* Remote Alarm indication Signal count */

	u16 sec;	/* One-second timer */

	u16 es;		/* Errored second */

	u16 rai;	/* remote alarm received */

	u16 bec;

	u16 fec;

	u16 cvc;

	u16 cec;

	u16 ebc;



	/* Status */

	ucchar red_alarm;

	ucchar blue_alarm;

	ucchar loss_fa;

	ucchar yellow_alarm;

	ucchar loss_mfa;

	ucchar prbs;

	u8 red_alarm;

	u8 blue_alarm;

	u8 loss_fa;

	u8 yellow_alarm;

	u8 loss_mfa;

	u8 prbs;

} falc_t;



typedef struct falc_status {

	ucchar sync;  /* If true FALC is synchronized */

	ucchar red_alarm;

	ucchar blue_alarm;

	ucchar loss_fa;

	ucchar yellow_alarm;

	ucchar loss_mfa;

	ucchar prbs;

	u8 sync;	/* If true FALC is synchronized */

	u8 red_alarm;

	u8 blue_alarm;

	u8 loss_fa;

	u8 yellow_alarm;

	u8 loss_mfa;

	u8 prbs;

} falc_status_t;



typedef struct rsv_x21_status {

	ucchar dcd;

	ucchar dsr;

	ucchar cts;

	ucchar rts;

	ucchar dtr;

	u8 dcd;

	u8 dsr;

	u8 cts;

	u8 rts;

	u8 dtr;

} rsv_x21_status_t;



typedef struct pc300stats {

	int hw_type;

	uclong line_on;

	uclong line_off;

	u32 line_on;

	u32 line_off;

	struct net_device_stats gen_stats;

	falc_t te_stats;

} pc300stats_t;
@@ -292,14 +288,14 @@ typedef struct pc300loopback { 


typedef struct pc300patterntst {

	char patrntst_on;       /* 0 - off; 1 - on; 2 - read num_errors */

	ucshort num_errors;

	u16 num_errors;

} pc300patterntst_t;



typedef struct pc300dev {

	struct pc300ch *chan;

	ucchar trace_on;

	uclong line_on;		/* DCD(X.21, RSV) / sync(TE) change counters */

	uclong line_off;

	u8 trace_on;

	u32 line_on;		/* DCD(X.21, RSV) / sync(TE) change counters */

	u32 line_off;

	char name[16];

	struct net_device *dev;

#ifdef CONFIG_PC300_MLPPP
@@ -312,42 +308,42 @@ typedef struct pc300hw { 
	int bus;		/* Bus (PCI, PMC, etc.) */

	int nchan;		/* number of channels */

	int irq;		/* interrupt request level */

	uclong clock;		/* Board clock */

	ucchar cpld_id;		/* CPLD ID (TE only) */

	ucshort cpld_reg1;	/* CPLD reg 1 (TE only) */

	ucshort cpld_reg2;	/* CPLD reg 2 (TE only) */

	ucshort gpioc_reg;	/* PLX GPIOC reg */

	ucshort intctl_reg;	/* PLX Int Ctrl/Status reg */

	uclong iophys;		/* PLX registers I/O base */

	uclong iosize;		/* PLX registers I/O size */

	uclong plxphys;		/* PLX registers MMIO base (physical) */

	u32 clock;		/* Board clock */

	u8 cpld_id;		/* CPLD ID (TE only) */

	u16 cpld_reg1;		/* CPLD reg 1 (TE only) */

	u16 cpld_reg2;		/* CPLD reg 2 (TE only) */

	u16 gpioc_reg;		/* PLX GPIOC reg */

	u16 intctl_reg;		/* PLX Int Ctrl/Status reg */

	u32 iophys;		/* PLX registers I/O base */

	u32 iosize;		/* PLX registers I/O size */

	u32 plxphys;		/* PLX registers MMIO base (physical) */

	void __iomem * plxbase;	/* PLX registers MMIO base (virtual) */

	uclong plxsize;		/* PLX registers MMIO size */

	uclong scaphys;		/* SCA registers MMIO base (physical) */

	u32 plxsize;		/* PLX registers MMIO size */

	u32 scaphys;		/* SCA registers MMIO base (physical) */

	void __iomem * scabase;	/* SCA registers MMIO base (virtual) */

	uclong scasize;		/* SCA registers MMIO size */

	uclong ramphys;		/* On-board RAM MMIO base (physical) */

	u32 scasize;		/* SCA registers MMIO size */

	u32 ramphys;		/* On-board RAM MMIO base (physical) */

	void __iomem * rambase;	/* On-board RAM MMIO base (virtual) */

	uclong alloc_ramsize;	/* RAM MMIO size allocated by the PCI bridge */

	uclong ramsize;		/* On-board RAM MMIO size */

	uclong falcphys;	/* FALC registers MMIO base (physical) */

	u32 alloc_ramsize;	/* RAM MMIO size allocated by the PCI bridge */

	u32 ramsize;		/* On-board RAM MMIO size */

	u32 falcphys;		/* FALC registers MMIO base (physical) */

	void __iomem * falcbase;/* FALC registers MMIO base (virtual) */

	uclong falcsize;	/* FALC registers MMIO size */

	u32 falcsize;		/* FALC registers MMIO size */

} pc300hw_t;



typedef struct pc300chconf {

	sync_serial_settings	phys_settings;	/* Clock type/rate (in bps),

						   loopback mode */

	raw_hdlc_proto		proto_settings;	/* Encoding, parity (CRC) */

	uclong media;		/* HW media (RS232, V.35, etc.) */

	uclong proto;		/* Protocol (PPP, X.25, etc.) */

	u32 media;		/* HW media (RS232, V.35, etc.) */

	u32 proto;		/* Protocol (PPP, X.25, etc.) */



	/* TE-specific parameters */

	ucchar lcode;		/* Line Code (AMI, B8ZS, etc.) */

	ucchar fr_mode;		/* Frame Mode (ESF, D4, etc.) */

	ucchar lbo;		/* Line Build Out */

	ucchar rx_sens;		/* Rx Sensitivity (long- or short-haul) */

	uclong tslot_bitmap;	/* bit[i]=1  =>  timeslot _i_ is active */

	u8 lcode;		/* Line Code (AMI, B8ZS, etc.) */

	u8 fr_mode;		/* Frame Mode (ESF, D4, etc.) */

	u8 lbo;			/* Line Build Out */

	u8 rx_sens;		/* Rx Sensitivity (long- or short-haul) */

	u32 tslot_bitmap;	/* bit[i]=1  =>  timeslot _i_ is active */

} pc300chconf_t;



typedef struct pc300ch {
@@ -355,11 +351,11 @@ typedef struct pc300ch { 
	int channel;

	pc300dev_t d;

	pc300chconf_t conf;

	ucchar tx_first_bd;	/* First TX DMA block descr. w/ data */

	ucchar tx_next_bd;	/* Next free TX DMA block descriptor */

	ucchar rx_first_bd;	/* First free RX DMA block descriptor */

	ucchar rx_last_bd;	/* Last free RX DMA block descriptor */

	ucchar nfree_tx_bd;	/* Number of free TX DMA block descriptors */

	u8 tx_first_bd;	/* First TX DMA block descr. w/ data */

	u8 tx_next_bd;	/* Next free TX DMA block descriptor */

	u8 rx_first_bd;	/* First free RX DMA block descriptor */

	u8 rx_last_bd;	/* Last free RX DMA block descriptor */

	u8 nfree_tx_bd;	/* Number of free TX DMA block descriptors */

	falc_t falc;	/* FALC structure (TE only) */

} pc300ch_t;

drivers/net/wan/pc300_drv.c

+60 −60
Original line number Diff line number Diff line
@@ -283,8 +283,8 @@ static void rx_dma_buf_init(pc300_t *, int); 
static void tx_dma_buf_check(pc300_t *, int);

static void rx_dma_buf_check(pc300_t *, int);

static irqreturn_t cpc_intr(int, void *);

static int clock_rate_calc(uclong, uclong, int *);

static uclong detect_ram(pc300_t *);

static int clock_rate_calc(u32, u32, int *);

static u32 detect_ram(pc300_t *);

static void plx_init(pc300_t *);

static void cpc_trace(struct net_device *, struct sk_buff *, char);

static int cpc_attach(struct net_device *, unsigned short, unsigned short);
@@ -309,10 +309,10 @@ static void tx_dma_buf_pt_init(pc300_t * card, int ch) 
			               + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));



	for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {

		cpc_writel(&ptdescr->next, (uclong) (DMA_TX_BD_BASE +

		cpc_writel(&ptdescr->next, (u32)(DMA_TX_BD_BASE +

			(ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));

		cpc_writel(&ptdescr->ptbuf,

						(uclong) (DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));

			   (u32)(DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));

	}

}
@@ -339,10 +339,10 @@ static void rx_dma_buf_pt_init(pc300_t * card, int ch) 
				       + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));



	for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {

		cpc_writel(&ptdescr->next, (uclong) (DMA_RX_BD_BASE +

		cpc_writel(&ptdescr->next, (u32)(DMA_RX_BD_BASE +

			(ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));

		cpc_writel(&ptdescr->ptbuf,

			   (uclong) (DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));

			   (u32)(DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));

	}

}
@@ -365,8 +365,8 @@ static void tx_dma_buf_check(pc300_t * card, int ch) 
{

	volatile pcsca_bd_t __iomem *ptdescr;

	int i;

	ucshort first_bd = card->chan[ch].tx_first_bd;

	ucshort next_bd = card->chan[ch].tx_next_bd;

	u16 first_bd = card->chan[ch].tx_first_bd;

	u16 next_bd = card->chan[ch].tx_next_bd;



	printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,

	       first_bd, TX_BD_ADDR(ch, first_bd),
@@ -390,9 +390,9 @@ static void tx1_dma_buf_check(pc300_t * card, int ch) 
{

	volatile pcsca_bd_t __iomem *ptdescr;

	int i;

	ucshort first_bd = card->chan[ch].tx_first_bd;

	ucshort next_bd = card->chan[ch].tx_next_bd;

	uclong scabase = card->hw.scabase;

	u16 first_bd = card->chan[ch].tx_first_bd;

	u16 next_bd = card->chan[ch].tx_next_bd;

	u32 scabase = card->hw.scabase;



	printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd);

	printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
@@ -416,8 +416,8 @@ static void rx_dma_buf_check(pc300_t * card, int ch) 
{

	volatile pcsca_bd_t __iomem *ptdescr;

	int i;

	ucshort first_bd = card->chan[ch].rx_first_bd;

	ucshort last_bd = card->chan[ch].rx_last_bd;

	u16 first_bd = card->chan[ch].rx_first_bd;

	u16 last_bd = card->chan[ch].rx_last_bd;

	int ch_factor;



	ch_factor = ch * N_DMA_RX_BUF;
@@ -438,9 +438,9 @@ static void rx_dma_buf_check(pc300_t * card, int ch) 
static int dma_get_rx_frame_size(pc300_t * card, int ch)

{

	volatile pcsca_bd_t __iomem *ptdescr;

	ucshort first_bd = card->chan[ch].rx_first_bd;

	u16 first_bd = card->chan[ch].rx_first_bd;

	int rcvd = 0;

	volatile ucchar status;

	volatile u8 status;



	ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));

	while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
@@ -460,12 +460,12 @@ static int dma_get_rx_frame_size(pc300_t * card, int ch) 
 * dma_buf_write: writes a frame to the Tx DMA buffers

 * NOTE: this function writes one frame at a time.

 */

static int dma_buf_write(pc300_t * card, int ch, ucchar * ptdata, int len)

static int dma_buf_write(pc300_t *card, int ch, u8 *ptdata, int len)

{

	int i, nchar;

	volatile pcsca_bd_t __iomem *ptdescr;

	int tosend = len;

	ucchar nbuf = ((len - 1) / BD_DEF_LEN) + 1;

	u8 nbuf = ((len - 1) / BD_DEF_LEN) + 1;



	if (nbuf >= card->chan[ch].nfree_tx_bd) {

		return -ENOMEM;
@@ -507,7 +507,7 @@ static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb) 
	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];

	volatile pcsca_bd_t __iomem *ptdescr;

	int rcvd = 0;

	volatile ucchar status;

	volatile u8 status;



	ptdescr = (card->hw.rambase +

				  RX_BD_ADDR(ch, chan->rx_first_bd));
@@ -561,8 +561,8 @@ static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb) 
static void tx_dma_stop(pc300_t * card, int ch)

{

	void __iomem *scabase = card->hw.scabase;

	ucchar drr_ena_bit = 1 << (5 + 2 * ch);

	ucchar drr_rst_bit = 1 << (1 + 2 * ch);

	u8 drr_ena_bit = 1 << (5 + 2 * ch);

	u8 drr_rst_bit = 1 << (1 + 2 * ch);



	/* Disable DMA */

	cpc_writeb(scabase + DRR, drr_ena_bit);
@@ -572,8 +572,8 @@ static void tx_dma_stop(pc300_t * card, int ch) 
static void rx_dma_stop(pc300_t * card, int ch)

{

	void __iomem *scabase = card->hw.scabase;

	ucchar drr_ena_bit = 1 << (4 + 2 * ch);

	ucchar drr_rst_bit = 1 << (2 * ch);

	u8 drr_ena_bit = 1 << (4 + 2 * ch);

	u8 drr_rst_bit = 1 << (2 * ch);



	/* Disable DMA */

	cpc_writeb(scabase + DRR, drr_ena_bit);
@@ -605,7 +605,7 @@ static void rx_dma_start(pc300_t * card, int ch) 
/*************************/

/***   FALC Routines   ***/

/*************************/

static void falc_issue_cmd(pc300_t * card, int ch, ucchar cmd)

static void falc_issue_cmd(pc300_t *card, int ch, u8 cmd)

{

	void __iomem *falcbase = card->hw.falcbase;

	unsigned long i = 0;
@@ -673,7 +673,7 @@ static void falc_intr_enable(pc300_t * card, int ch) 
static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)

{

	void __iomem *falcbase = card->hw.falcbase;

	ucchar tshf = card->chan[ch].falc.offset;

	u8 tshf = card->chan[ch].falc.offset;



	cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),

		   cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
@@ -689,7 +689,7 @@ static void falc_open_timeslot(pc300_t * card, int ch, int timeslot) 
static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)

{

	void __iomem *falcbase = card->hw.falcbase;

	ucchar tshf = card->chan[ch].falc.offset;

	u8 tshf = card->chan[ch].falc.offset;



	cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),

		   cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
@@ -810,7 +810,7 @@ static void falc_init_t1(pc300_t * card, int ch) 
	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;

	falc_t *pfalc = (falc_t *) & chan->falc;

	void __iomem *falcbase = card->hw.falcbase;

	ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);

	u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);



	/* Switch to T1 mode (PCM 24) */

	cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
@@ -979,7 +979,7 @@ static void falc_init_e1(pc300_t * card, int ch) 
	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;

	falc_t *pfalc = (falc_t *) & chan->falc;

	void __iomem *falcbase = card->hw.falcbase;

	ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);

	u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);



	/* Switch to E1 mode (PCM 30) */

	cpc_writeb(falcbase + F_REG(FMR1, ch),
@@ -1185,7 +1185,7 @@ static void te_config(pc300_t * card, int ch) 
	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;

	falc_t *pfalc = (falc_t *) & chan->falc;

	void __iomem *falcbase = card->hw.falcbase;

	ucchar dummy;

	u8 dummy;

	unsigned long flags;



	memset(pfalc, 0, sizeof(falc_t));
@@ -1401,7 +1401,7 @@ static void falc_update_stats(pc300_t * card, int ch) 
	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;

	falc_t *pfalc = (falc_t *) & chan->falc;

	void __iomem *falcbase = card->hw.falcbase;

	ucshort counter;

	u16 counter;



	counter = cpc_readb(falcbase + F_REG(FECL, ch));

	counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
@@ -1727,7 +1727,7 @@ static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate) 
 * Description:	This routine returns the bit error counter value

 *----------------------------------------------------------------------------

 */

static ucshort falc_pattern_test_error(pc300_t * card, int ch)

static u16 falc_pattern_test_error(pc300_t * card, int ch)

{

	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];

	falc_t *pfalc = (falc_t *) & chan->falc;
@@ -1774,7 +1774,7 @@ static void cpc_tx_timeout(struct net_device *dev) 
	pc300_t *card = (pc300_t *) chan->card;

	int ch = chan->channel;

	unsigned long flags;

	ucchar ilar;

	u8 ilar;



	dev->stats.tx_errors++;

	dev->stats.tx_aborted_errors++;
@@ -1830,7 +1830,7 @@ static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev) 
	}



	/* Write buffer to DMA buffers */

	if (dma_buf_write(card, ch, (ucchar *) skb->data, skb->len) != 0) {

	if (dma_buf_write(card, ch, (u8 *)skb->data, skb->len) != 0) {

//		printk("%s: write error. Dropping TX packet.\n", dev->name);

		netif_stop_queue(dev);

		dev_kfree_skb(skb);
@@ -1995,7 +1995,7 @@ static void sca_tx_intr(pc300dev_t *dev) 
static void sca_intr(pc300_t * card)

{

	void __iomem *scabase = card->hw.scabase;

	volatile uclong status;

	volatile u32 status;

	int ch;

	int intr_count = 0;

	unsigned char dsr_rx;
@@ -2010,7 +2010,7 @@ static void sca_intr(pc300_t * card) 


	    /**** Reception ****/

			if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {

				ucchar drx_stat = cpc_readb(scabase + DSR_RX(ch));

				u8 drx_stat = cpc_readb(scabase + DSR_RX(ch));



				/* Clear RX interrupts */

				cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
@@ -2084,7 +2084,7 @@ static void sca_intr(pc300_t * card) 


	    /**** Transmission ****/

			if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {

				ucchar dtx_stat = cpc_readb(scabase + DSR_TX(ch));

				u8 dtx_stat = cpc_readb(scabase + DSR_TX(ch));



				/* Clear TX interrupts */

				cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
@@ -2128,7 +2128,7 @@ static void sca_intr(pc300_t * card) 


	    /**** MSCI ****/

			if (status & IR0_M(IR0_RXINTA, ch)) {

				ucchar st1 = cpc_readb(scabase + M_REG(ST1, ch));

				u8 st1 = cpc_readb(scabase + M_REG(ST1, ch));



				/* Clear MSCI interrupts */

				cpc_writeb(scabase + M_REG(ST1, ch), st1);
@@ -2170,7 +2170,7 @@ static void sca_intr(pc300_t * card) 
	}

}



static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1)

static void falc_t1_loop_detection(pc300_t *card, int ch, u8 frs1)

{

	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];

	falc_t *pfalc = (falc_t *) & chan->falc;
@@ -2195,7 +2195,7 @@ static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1) 
	}

}



static void falc_e1_loop_detection(pc300_t * card, int ch, ucchar rsp)

static void falc_e1_loop_detection(pc300_t *card, int ch, u8 rsp)

{

	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];

	falc_t *pfalc = (falc_t *) & chan->falc;
@@ -2225,8 +2225,8 @@ static void falc_t1_intr(pc300_t * card, int ch) 
	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];

	falc_t *pfalc = (falc_t *) & chan->falc;

	void __iomem *falcbase = card->hw.falcbase;

	ucchar isr0, isr3, gis;

	ucchar dummy;

	u8 isr0, isr3, gis;

	u8 dummy;



	while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {

		if (gis & GIS_ISR0) {
@@ -2272,8 +2272,8 @@ static void falc_e1_intr(pc300_t * card, int ch) 
	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];

	falc_t *pfalc = (falc_t *) & chan->falc;

	void __iomem *falcbase = card->hw.falcbase;

	ucchar isr1, isr2, isr3, gis, rsp;

	ucchar dummy;

	u8 isr1, isr2, isr3, gis, rsp;

	u8 dummy;



	while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {

		rsp = cpc_readb(falcbase + F_REG(RSP, ch));
@@ -2355,7 +2355,7 @@ static void falc_intr(pc300_t * card) 
static irqreturn_t cpc_intr(int irq, void *dev_id)

{

	pc300_t *card = dev_id;

	volatile ucchar plx_status;

	volatile u8 plx_status;



	if (!card) {

#ifdef PC300_DEBUG_INTR
@@ -2394,7 +2394,7 @@ static irqreturn_t cpc_intr(int irq, void *dev_id) 


static void cpc_sca_status(pc300_t * card, int ch)

{

	ucchar ilar;

	u8 ilar;

	void __iomem *scabase = card->hw.scabase;

	unsigned long flags;
@@ -2812,7 +2812,7 @@ static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 
	}

}



static int clock_rate_calc(uclong rate, uclong clock, int *br_io)

static int clock_rate_calc(u32 rate, u32 clock, int *br_io)

{

	int br, tc;

	int br_pwr, error;
@@ -2849,11 +2849,11 @@ static int ch_config(pc300dev_t * d) 
	void __iomem *scabase = card->hw.scabase;

	void __iomem *plxbase = card->hw.plxbase;

	int ch = chan->channel;

	uclong clkrate = chan->conf.phys_settings.clock_rate;

	uclong clktype = chan->conf.phys_settings.clock_type;

	ucshort encoding = chan->conf.proto_settings.encoding;

	ucshort parity = chan->conf.proto_settings.parity;   

	ucchar md0, md2;

	u32 clkrate = chan->conf.phys_settings.clock_rate;

	u32 clktype = chan->conf.phys_settings.clock_type;

	u16 encoding = chan->conf.proto_settings.encoding;

	u16 parity = chan->conf.proto_settings.parity;

	u8 md0, md2;



	/* Reset the channel */

	cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
@@ -3193,16 +3193,16 @@ static int cpc_close(struct net_device *dev) 
	return 0;

}



static uclong detect_ram(pc300_t * card)

static u32 detect_ram(pc300_t * card)

{

	uclong i;

	ucchar data;

	u32 i;

	u8 data;

	void __iomem *rambase = card->hw.rambase;



	card->hw.ramsize = PC300_RAMSIZE;

	/* Let's find out how much RAM is present on this board */

	for (i = 0; i < card->hw.ramsize; i++) {

		data = (ucchar) (i & 0xff);

		data = (u8)(i & 0xff);

		cpc_writeb(rambase + i, data);

		if (cpc_readb(rambase + i) != data) {

			break;
@@ -3279,7 +3279,7 @@ static void cpc_init_card(pc300_t * card) 
	cpc_writeb(card->hw.scabase + DMER, 0x80);



	if (card->hw.type == PC300_TE) {

		ucchar reg1;

		u8 reg1;



		/* Check CPLD version */

		reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
@@ -3413,7 +3413,7 @@ cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 
{

	static int first_time = 1;

	int err, eeprom_outdated = 0;

	ucshort device_id;

	u16 device_id;

	pc300_t *card;



	if (first_time) {