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Commit b210aeae authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'stmmac-pci-fix-crash-on-Intel-Galileo-Gen2' 



Andy Shevchenko says:

====================
stmmac: pci: Fix crash on Intel Galileo Gen2

Due to misconfiguration of PCI driver for Intel Quark the user will get
a kernel crash:

udhcpc: started, v1.26.2
stmmaceth 0000:00:14.6 eth0: device MAC address 98:4f:ee:05:ac:47
Generic PHY stmmac-a6:01: attached PHY driver [Generic PHY] (mii_bus:phy_addr=stmmac-a6:01, irq=-1)
stmmaceth 0000:00:14.6 eth0: IEEE 1588-2008 Advanced Timestamp supported
stmmaceth 0000:00:14.6 eth0: registered PTP clock
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready

udhcpc: sending discover

stmmaceth 0000:00:14.6 eth0: Link is Up - 100Mbps/Full - flow control off
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
BUG: unable to handle kernel NULL pointer dereference at (null)
IP: stmmac_xmit+0xf1/0x1080

Fix this by adding necessary settings.

P.S. I split fix to three patches according to what each of them adds.
====================

Tested-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 8ed508fd 70fe4432

drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c

+18 −23
Original line number Diff line number Diff line
@@ -70,11 +70,8 @@ static int stmmac_pci_find_phy_addr(struct stmmac_pci_info *info) 
	return -ENODEV;

}



static void stmmac_default_data(struct plat_stmmacenet_data *plat)

static void common_default_data(struct plat_stmmacenet_data *plat)

{

	plat->bus_id = 1;

	plat->phy_addr = 0;

	plat->interface = PHY_INTERFACE_MODE_GMII;

	plat->clk_csr = 2;	/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */

	plat->has_gmac = 1;

	plat->force_sf_dma_mode = 1;
@@ -82,10 +79,6 @@ static void stmmac_default_data(struct plat_stmmacenet_data *plat) 
	plat->mdio_bus_data->phy_reset = NULL;

	plat->mdio_bus_data->phy_mask = 0;



	plat->dma_cfg->pbl = 32;

	plat->dma_cfg->pblx8 = true;

	/* TODO: AXI */



	/* Set default value for multicast hash bins */

	plat->multicast_filter_bins = HASH_TABLE_SIZE;
@@ -107,12 +100,29 @@ static void stmmac_default_data(struct plat_stmmacenet_data *plat) 
	plat->rx_queues_cfg[0].pkt_route = 0x0;

}



static void stmmac_default_data(struct plat_stmmacenet_data *plat)

{

	/* Set common default data first */

	common_default_data(plat);



	plat->bus_id = 1;

	plat->phy_addr = 0;

	plat->interface = PHY_INTERFACE_MODE_GMII;



	plat->dma_cfg->pbl = 32;

	plat->dma_cfg->pblx8 = true;

	/* TODO: AXI */

}



static int quark_default_data(struct plat_stmmacenet_data *plat,

			      struct stmmac_pci_info *info)

{

	struct pci_dev *pdev = info->pdev;

	int ret;



	/* Set common default data first */

	common_default_data(plat);



	/*

	 * Refuse to load the driver and register net device if MAC controller

	 * does not connect to any PHY interface.
@@ -124,27 +134,12 @@ static int quark_default_data(struct plat_stmmacenet_data *plat, 
	plat->bus_id = PCI_DEVID(pdev->bus->number, pdev->devfn);

	plat->phy_addr = ret;

	plat->interface = PHY_INTERFACE_MODE_RMII;

	plat->clk_csr = 2;

	plat->has_gmac = 1;

	plat->force_sf_dma_mode = 1;



	plat->mdio_bus_data->phy_reset = NULL;

	plat->mdio_bus_data->phy_mask = 0;



	plat->dma_cfg->pbl = 16;

	plat->dma_cfg->pblx8 = true;

	plat->dma_cfg->fixed_burst = 1;

	/* AXI (TODO) */



	/* Set default value for multicast hash bins */

	plat->multicast_filter_bins = HASH_TABLE_SIZE;



	/* Set default value for unicast filter entries */

	plat->unicast_filter_entries = 1;



	/* Set the maxmtu to a default of JUMBO_LEN */

	plat->maxmtu = JUMBO_LEN;



	return 0;

}