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Commit b1bb8c01 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Introduce new read/write macros for SOC15 



Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 93ea9b9f

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −3
Original line number Diff line number Diff line
@@ -1704,9 +1704,6 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 
#define WREG32_FIELD_OFFSET(reg, offset, field, val)	\

	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))



#define WREG32_FIELD15(ip, idx, reg, field, val)	\

	WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))



/*

 * BIOS helpers.

 */

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+19 −1
Original line number Diff line number Diff line
@@ -45,13 +45,31 @@ struct nbio_pcie_index_data { 
	u32 index_offset;

	u32 data_offset;

};

// Register Access Macro



/* Register Access Macros */

#define SOC15_REG_OFFSET(ip, inst, reg)       (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \

                                                (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \

                                                    (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \

                                                        (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \

                                                            (ip##_BASE__INST##inst##_SEG4 + reg)))))



#define WREG32_FIELD15(ip, idx, reg, field, val)	\

	WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))



#define RREG32_SOC15(ip, inst, reg) \

	RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \

		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \

		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \

		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \

		(ip##_BASE__INST##inst##_SEG4 + reg))))))



#define WREG32_SOC15(ip, inst, reg, value) \

	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \

		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \

		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \

		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \

		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)



#endif