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Commit b1a6d3ec authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by David S. Miller
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defxx: DEFEA's Burst Holdoff register initialization fix 



Use the mask rather than bit number macro to initialize the chip select
control bit for PDQ register space decoding in the Burst Holdoff register.

Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8a189f12

drivers/net/fddi/defxx.c

+2 −2
Original line number Diff line number Diff line
@@ -748,9 +748,9 @@ static void dfx_bus_init(struct net_device *dev) 
		 */

		val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF);

		if (dfx_use_mmio)

			val |= PI_BURST_HOLDOFF_V_MEM_MAP;

			val |= PI_BURST_HOLDOFF_M_MEM_MAP;

		else

			val &= ~PI_BURST_HOLDOFF_V_MEM_MAP;

			val &= ~PI_BURST_HOLDOFF_M_MEM_MAP;

		outb(val, base_addr + PI_DEFEA_K_BURST_HOLDOFF);



		/* Enable interrupts at EISA bus interface chip (ESIC) */