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Commit b189817c authored by Horia Geantă's avatar Horia Geantă Committed by Herbert Xu
Browse files

crypto: caam/qi - add ablkcipher and authenc algorithms 



Add support to submit ablkcipher and authenc algorithms
via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede}))
authenc(hmac(sha*),cbc({aes,des,des3_ede}))

caam/qi being a new driver, let's wait some time to settle down without
interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are
marked to be of lower priority than caam/jr ones (caamalg module).

Signed-off-by: default avatarVakul Garg <vakul.garg@nxp.com>
Signed-off-by: default avatarAlex Porosanu <alexandru.porosanu@nxp.com>
Signed-off-by: default avatarHoria Geantă <horia.geanta@nxp.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 67c2315d

drivers/crypto/caam/Kconfig

+19 −1
Original line number Diff line number Diff line
@@ -87,6 +87,23 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API 
	  To compile this as a module, choose M here: the module

	  will be called caamalg.



config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI

	tristate "Queue Interface as Crypto API backend"

	depends on CRYPTO_DEV_FSL_CAAM_JR && FSL_DPAA && NET

	default y

	select CRYPTO_AUTHENC

	select CRYPTO_BLKCIPHER

	help

	  Selecting this will use CAAM Queue Interface (QI) for sending

	  & receiving crypto jobs to/from CAAM. This gives better performance

	  than job ring interface when the number of cores are more than the

	  number of job rings assigned to the kernel. The number of portals

	  assigned to the kernel should also be more than the number of

	  job rings.



	  To compile this as a module, choose M here: the module

	  will be called caamalg_qi.



config CRYPTO_DEV_FSL_CAAM_AHASH_API

	tristate "Register hash algorithm implementations with Crypto API"

	depends on CRYPTO_DEV_FSL_CAAM_JR
@@ -136,4 +153,5 @@ config CRYPTO_DEV_FSL_CAAM_DEBUG 
	  information in the CAAM driver.



config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC

	def_tristate CRYPTO_DEV_FSL_CAAM_CRYPTO_API
 
	def_tristate (CRYPTO_DEV_FSL_CAAM_CRYPTO_API || \

		      CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI)

drivers/crypto/caam/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ endif 
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o

drivers/crypto/caam/caamalg.c

+5 −4
Original line number Diff line number Diff line
@@ -266,8 +266,9 @@ static int aead_set_sh_desc(struct crypto_aead *aead) 


	/* aead_encrypt shared descriptor */

	desc = ctx->sh_desc_enc;

	cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ctx->authsize,

			       is_rfc3686, nonce, ctx1_iv_off);

	cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ivsize,

			       ctx->authsize, is_rfc3686, nonce, ctx1_iv_off,

			       false);

	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,

				   desc_bytes(desc), DMA_TO_DEVICE);
@@ -299,7 +300,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead) 
	desc = ctx->sh_desc_dec;

	cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize,

			       ctx->authsize, alg->caam.geniv, is_rfc3686,

			       nonce, ctx1_iv_off);

			       nonce, ctx1_iv_off, false);

	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,

				   desc_bytes(desc), DMA_TO_DEVICE);
@@ -333,7 +334,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead) 
	desc = ctx->sh_desc_enc;

	cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize,

				  ctx->authsize, is_rfc3686, nonce,

				  ctx1_iv_off);

				  ctx1_iv_off, false);

	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,

				   desc_bytes(desc), DMA_TO_DEVICE);

drivers/crypto/caam/caamalg_desc.c

+71 −6
Original line number Diff line number Diff line
@@ -265,17 +265,19 @@ static void init_sh_desc_key_aead(u32 * const desc, 
 *         split key is to be used, the size of the split key itself is

 *         specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1,

 *         SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP.

 * @ivsize: initialization vector size

 * @icvsize: integrity check value (ICV) size (truncated or full)

 * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template

 * @nonce: pointer to rfc3686 nonce

 * @ctx1_iv_off: IV offset in CONTEXT1 register

 * @is_qi: true when called from caam/qi

 *

 * Note: Requires an MDHA split key.

 */

void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,

			    struct alginfo *adata, unsigned int icvsize,

			    const bool is_rfc3686, u32 *nonce,

			    const u32 ctx1_iv_off)

			    struct alginfo *adata, unsigned int ivsize,

			    unsigned int icvsize, const bool is_rfc3686,

			    u32 *nonce, const u32 ctx1_iv_off, const bool is_qi)

{

	/* Note: Context registers are saved. */

	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
@@ -284,6 +286,25 @@ void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata, 
	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |

			 OP_ALG_ENCRYPT);



	if (is_qi) {

		u32 *wait_load_cmd;



		/* REG3 = assoclen */

		append_seq_load(desc, 4, LDST_CLASS_DECO |

				LDST_SRCDST_WORD_DECO_MATH3 |

				(4 << LDST_OFFSET_SHIFT));



		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |

					    JUMP_COND_CALM | JUMP_COND_NCP |

					    JUMP_COND_NOP | JUMP_COND_NIP |

					    JUMP_COND_NIFP);

		set_jump_tgt_here(desc, wait_load_cmd);



		append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |

				LDST_SRCDST_BYTE_CONTEXT |

				(ctx1_iv_off << LDST_OFFSET_SHIFT));

	}



	/* Read and write assoclen bytes */

	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);

	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
@@ -338,6 +359,7 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_encap); 
 * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template

 * @nonce: pointer to rfc3686 nonce

 * @ctx1_iv_off: IV offset in CONTEXT1 register

 * @is_qi: true when called from caam/qi

 *

 * Note: Requires an MDHA split key.

 */
@@ -345,7 +367,7 @@ void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata, 
			    struct alginfo *adata, unsigned int ivsize,

			    unsigned int icvsize, const bool geniv,

			    const bool is_rfc3686, u32 *nonce,

			    const u32 ctx1_iv_off)

			    const u32 ctx1_iv_off, const bool is_qi)

{

	/* Note: Context registers are saved. */

	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
@@ -354,6 +376,26 @@ void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata, 
	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |

			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);



	if (is_qi) {

		u32 *wait_load_cmd;



		/* REG3 = assoclen */

		append_seq_load(desc, 4, LDST_CLASS_DECO |

				LDST_SRCDST_WORD_DECO_MATH3 |

				(4 << LDST_OFFSET_SHIFT));



		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |

					    JUMP_COND_CALM | JUMP_COND_NCP |

					    JUMP_COND_NOP | JUMP_COND_NIP |

					    JUMP_COND_NIFP);

		set_jump_tgt_here(desc, wait_load_cmd);



		if (!geniv)

			append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |

					LDST_SRCDST_BYTE_CONTEXT |

					(ctx1_iv_off << LDST_OFFSET_SHIFT));

	}



	/* Read and write assoclen bytes */

	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);

	if (geniv)
@@ -423,21 +465,44 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_decap); 
 * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template

 * @nonce: pointer to rfc3686 nonce

 * @ctx1_iv_off: IV offset in CONTEXT1 register

 * @is_qi: true when called from caam/qi

 *

 * Note: Requires an MDHA split key.

 */

void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,

			       struct alginfo *adata, unsigned int ivsize,

			       unsigned int icvsize, const bool is_rfc3686,

			       u32 *nonce, const u32 ctx1_iv_off)

			       u32 *nonce, const u32 ctx1_iv_off,

			       const bool is_qi)

{

	u32 geniv, moveiv;



	/* Note: Context registers are saved. */

	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);



	if (is_rfc3686)

	if (is_qi) {

		u32 *wait_load_cmd;



		/* REG3 = assoclen */

		append_seq_load(desc, 4, LDST_CLASS_DECO |

				LDST_SRCDST_WORD_DECO_MATH3 |

				(4 << LDST_OFFSET_SHIFT));



		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |

					    JUMP_COND_CALM | JUMP_COND_NCP |

					    JUMP_COND_NOP | JUMP_COND_NIP |

					    JUMP_COND_NIFP);

		set_jump_tgt_here(desc, wait_load_cmd);

	}



	if (is_rfc3686) {

		if (is_qi)

			append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |

					LDST_SRCDST_BYTE_CONTEXT |

					(ctx1_iv_off << LDST_OFFSET_SHIFT));



		goto copy_iv;

	}



	/* Generate IV */

	geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |

drivers/crypto/caam/caamalg_desc.h

+10 −5
Original line number Diff line number Diff line
@@ -12,6 +12,9 @@ 
#define DESC_AEAD_ENC_LEN		(DESC_AEAD_BASE + 11 * CAAM_CMD_SZ)

#define DESC_AEAD_DEC_LEN		(DESC_AEAD_BASE + 15 * CAAM_CMD_SZ)

#define DESC_AEAD_GIVENC_LEN		(DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)

#define DESC_QI_AEAD_ENC_LEN		(DESC_AEAD_ENC_LEN + 3 * CAAM_CMD_SZ)

#define DESC_QI_AEAD_DEC_LEN		(DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ)

#define DESC_QI_AEAD_GIVENC_LEN		(DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ)



/* Note: Nonce is counted in cdata.keylen */

#define DESC_AEAD_CTR_RFC3686_LEN	(4 * CAAM_CMD_SZ)
@@ -45,20 +48,22 @@ void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata, 
				 unsigned int icvsize);



void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,

			    struct alginfo *adata, unsigned int icvsize,

			    const bool is_rfc3686, u32 *nonce,

			    const u32 ctx1_iv_off);

			    struct alginfo *adata, unsigned int ivsize,

			    unsigned int icvsize, const bool is_rfc3686,

			    u32 *nonce, const u32 ctx1_iv_off,

			    const bool is_qi);



void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,

			    struct alginfo *adata, unsigned int ivsize,

			    unsigned int icvsize, const bool geniv,

			    const bool is_rfc3686, u32 *nonce,

			    const u32 ctx1_iv_off);

			    const u32 ctx1_iv_off, const bool is_qi);



void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,

			       struct alginfo *adata, unsigned int ivsize,

			       unsigned int icvsize, const bool is_rfc3686,

			       u32 *nonce, const u32 ctx1_iv_off);

			       u32 *nonce, const u32 ctx1_iv_off,

			       const bool is_qi);



void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata,

			   unsigned int icvsize);