Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 11 SUBLEVEL = 0 EXTRAVERSION = -rc7 EXTRAVERSION = -rc8 NAME = Fearless Coyote # *DOCUMENTATION* Loading arch/arc/Kconfig +8 −0 Original line number Diff line number Diff line Loading @@ -406,6 +406,14 @@ config ARC_HAS_DIV_REM bool "Insn: div, divu, rem, remu" default y config ARC_HAS_ACCL_REGS bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" default n help Depending on the configuration, CPU can contain accumulator reg-pair (also referred to as r58:r59). These can also be used by gcc as GPR so kernel needs to save/restore per process endif # ISA_ARCV2 endmenu # "ARC CPU Configuration" Loading arch/arc/include/asm/atomic.h +2 −1 Original line number Diff line number Diff line Loading @@ -17,10 +17,11 @@ #include <asm/barrier.h> #include <asm/smp.h> #define ATOMIC_INIT(i) { (i) } #ifndef CONFIG_ARC_PLAT_EZNPS #define atomic_read(v) READ_ONCE((v)->counter) #define ATOMIC_INIT(i) { (i) } #ifdef CONFIG_ARC_HAS_LLSC Loading arch/arc/include/asm/entry-arcv2.h +10 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,11 @@ ; ; Now manually save: r12, sp, fp, gp, r25 #ifdef CONFIG_ARC_HAS_ACCL_REGS PUSH r59 PUSH r58 #endif PUSH r30 PUSH r12 Loading Loading @@ -75,6 +80,11 @@ POP r12 POP r30 #ifdef CONFIG_ARC_HAS_ACCL_REGS POP r58 POP r59 #endif .endm /*------------------------------------------------------------------------*/ Loading arch/arc/include/asm/ptrace.h +4 −0 Original line number Diff line number Diff line Loading @@ -86,6 +86,10 @@ struct pt_regs { unsigned long r12, r30; #ifdef CONFIG_ARC_HAS_ACCL_REGS unsigned long r58, r59; /* ACCL/ACCH used by FPU / DSP MPY */ #endif /*------- Below list auto saved by h/w -----------*/ unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11; Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 11 SUBLEVEL = 0 EXTRAVERSION = -rc7 EXTRAVERSION = -rc8 NAME = Fearless Coyote # *DOCUMENTATION* Loading
arch/arc/Kconfig +8 −0 Original line number Diff line number Diff line Loading @@ -406,6 +406,14 @@ config ARC_HAS_DIV_REM bool "Insn: div, divu, rem, remu" default y config ARC_HAS_ACCL_REGS bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" default n help Depending on the configuration, CPU can contain accumulator reg-pair (also referred to as r58:r59). These can also be used by gcc as GPR so kernel needs to save/restore per process endif # ISA_ARCV2 endmenu # "ARC CPU Configuration" Loading
arch/arc/include/asm/atomic.h +2 −1 Original line number Diff line number Diff line Loading @@ -17,10 +17,11 @@ #include <asm/barrier.h> #include <asm/smp.h> #define ATOMIC_INIT(i) { (i) } #ifndef CONFIG_ARC_PLAT_EZNPS #define atomic_read(v) READ_ONCE((v)->counter) #define ATOMIC_INIT(i) { (i) } #ifdef CONFIG_ARC_HAS_LLSC Loading
arch/arc/include/asm/entry-arcv2.h +10 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,11 @@ ; ; Now manually save: r12, sp, fp, gp, r25 #ifdef CONFIG_ARC_HAS_ACCL_REGS PUSH r59 PUSH r58 #endif PUSH r30 PUSH r12 Loading Loading @@ -75,6 +80,11 @@ POP r12 POP r30 #ifdef CONFIG_ARC_HAS_ACCL_REGS POP r58 POP r59 #endif .endm /*------------------------------------------------------------------------*/ Loading
arch/arc/include/asm/ptrace.h +4 −0 Original line number Diff line number Diff line Loading @@ -86,6 +86,10 @@ struct pt_regs { unsigned long r12, r30; #ifdef CONFIG_ARC_HAS_ACCL_REGS unsigned long r58, r59; /* ACCL/ACCH used by FPU / DSP MPY */ #endif /*------- Below list auto saved by h/w -----------*/ unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11; Loading