Loading arch/powerpc/kernel/traps.c +10 −2 Original line number Diff line number Diff line Loading @@ -437,6 +437,7 @@ static inline int check_io_access(struct pt_regs *regs) int machine_check_e500mc(struct pt_regs *regs) { unsigned long mcsr = mfspr(SPRN_MCSR); unsigned long pvr = mfspr(SPRN_PVR); unsigned long reason = mcsr; int recoverable = 1; Loading Loading @@ -478,9 +479,16 @@ int machine_check_e500mc(struct pt_regs *regs) * may still get logged and cause a machine check. We should * only treat the non-write shadow case as non-recoverable. */ /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit * is not implemented but L1 data cache always runs in write * shadow mode. Hence on data cache parity errors HW will * automatically invalidate the L1 Data Cache. */ if (PVR_VER(pvr) != PVR_VER_E6500) { if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) recoverable = 0; } } if (reason & MCSR_L2MMU_MHIT) { printk("Hit on multiple TLB entries\n"); Loading Loading
arch/powerpc/kernel/traps.c +10 −2 Original line number Diff line number Diff line Loading @@ -437,6 +437,7 @@ static inline int check_io_access(struct pt_regs *regs) int machine_check_e500mc(struct pt_regs *regs) { unsigned long mcsr = mfspr(SPRN_MCSR); unsigned long pvr = mfspr(SPRN_PVR); unsigned long reason = mcsr; int recoverable = 1; Loading Loading @@ -478,9 +479,16 @@ int machine_check_e500mc(struct pt_regs *regs) * may still get logged and cause a machine check. We should * only treat the non-write shadow case as non-recoverable. */ /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit * is not implemented but L1 data cache always runs in write * shadow mode. Hence on data cache parity errors HW will * automatically invalidate the L1 Data Cache. */ if (PVR_VER(pvr) != PVR_VER_E6500) { if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) recoverable = 0; } } if (reason & MCSR_L2MMU_MHIT) { printk("Hit on multiple TLB entries\n"); Loading