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Commit b12c5805 authored by Harigovindan P's avatar Harigovindan P Committed by Gerrit - the friendly Code Review server
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disp: pll: Add support for 7nm C-PHY shadow clock 



Add support for 7nm DSI PLL C-PHY shadow clocks, which
will be used during dynamic dsi clock switch.

Change-Id: Iac131b9085d5541434f8480c14e7de4c8d014d2e
Signed-off-by: default avatarHarigovindan P <harigovi@codeaurora.org>
parent 3a64d56d

pll/dsi_pll_7nm.c

+157 −22
Original line number Diff line number Diff line
@@ -1136,7 +1136,8 @@ static void shadow_dsi_pll_dynamic_refresh_7nm(struct dsi_pll_7nm *pll, 
	MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL6,

			   (PLL_CMODE_1 + offset),

			   (PLL_CLOCK_INVERTERS_1 + offset),

			   0x10, reg->pll_clock_inverters);

			    pll->cphy_enabled ? 0x00 : 0x10,

			    reg->pll_clock_inverters);

	upper_addr |=

		(upper_8_bit(PLL_CMODE_1 + offset) << 12);

	upper_addr |= (upper_8_bit(PLL_CLOCK_INVERTERS_1 + offset) << 13);
@@ -1616,6 +1617,11 @@ static unsigned long vco_7nm_recalc_rate(struct clk_hw *hw, 
		return 0;

	}



	if (!pll->priv) {

		pr_err("pll priv is null\n");

		return 0;

	}



	/*

	 * In the case when vco arte is set, the recalculation function should

	 * return the current rate as to avoid trying to set the vco rate
@@ -1635,6 +1641,7 @@ static unsigned long vco_7nm_recalc_rate(struct clk_hw *hw, 
	}



	pll->handoff_resources = true;

	dsi_pll_detect_phy_mode(pll->priv, pll);

	if (dsi_pll_7nm_lock_status(pll)) {

		pr_debug("PLL not enabled\n");

		pll->handoff_resources = false;
@@ -1843,25 +1850,25 @@ static struct regmap_bus mdss_mux_regmap_bus = { 
 *      |  DIV(8)   |  |  DIV(7)   |   |  |   DIV (2)   | | |   DIV(4)   |  |  DIV(3.5)  |

 *      +-----+-----+  +-----+-----+   |  +------+------+ | +-----+------+  +------+-----+

 *            |              |         |         |        |       |                |

 *Shadow Path |          CPHY Path     |         |        |       |           +----v

 *     +      |              |         +------+  |        |   +---+           |

 *     +---+  |        +-----+                |  |        |   |               |

 *         |  |        |                    +-v--v----v---v---+      +--------v--------+

 *     +---v--v--------v---+                 \  pclk_src_mux /        \ cphy_pclk_src /

 *Shadow DPHY | Shadow   CPHY Path     |         |        |       |           +----v

 *    Path    | CPHY Path    |         +------+  |        |   +---+           |

 *     +---+  |    |   +-----+                |  |        |   |               |

 *         |  |    |   |                    +-v--v----v---v---+      +--------v--------+

 *     +---v--v----v---v---+                 \  pclk_src_mux /        \ cphy_pclk_src /

 *      \   byteclk_mux   /                   \             /          \     mux     /

 *       \               /                     +-----+-----+            +-----+-----+

 *        +------+------+                            |      Shadow Path       |

 *               |                                   |           +            |

 *        +------+------+                            |         Shadow         |

 *               |                                   |        DPHY Path       |

 *               v                             +-----v------+    |     +------v------+

 *         dsi_byte_clk                        |  pclk_src  |    |     |cphy_pclk_src|

 *                                             | DIV(1..15) |    |     |  DIV(1..15) |

 *                                             +-----+------+    |     +------+------+

 *                                                   |           |            |

 *                                                   |           |        CPHY Path

 *                                                   |           |            |

 *                                                   +-------+   |    +-------+

 *                                                           |   |    |

 *                                                       +---v---v----v------+

 *                                                   |           |            |     Shadow CPHY Path

 *                                                   +-------+   |    +-------+           |

 *                                                           |   |    |   |----------------

 *                                                       +---v---v----v---v--+

 *                                                        \     pclk_mux    /

 *                                                          +------+------+

 *                                                                 |
@@ -2090,6 +2097,17 @@ static struct clk_fixed_factor dsi0pll_post_vco_div3_5 = { 
	},

};



static struct clk_fixed_factor dsi0pll_shadow_post_vco_div3_5 = {

	.div = 7,

	.mult = 2,

	.hw.init = &(struct clk_init_data){

		.name = "dsi0pll_shadow_post_vco_div3_5",

		.parent_names = (const char *[]){"dsi0pll_shadow_pll_out_div"},

		.num_parents = 1,

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi1pll_post_vco_div3_5 = {

	.div = 7,

	.mult = 2,
@@ -2101,6 +2119,17 @@ static struct clk_fixed_factor dsi1pll_post_vco_div3_5 = { 
	},

};



static struct clk_fixed_factor dsi1pll_shadow_post_vco_div3_5 = {

	.div = 7,

	.mult = 2,

	.hw.init = &(struct clk_init_data){

		.name = "dsi1pll_shadow_post_vco_div3_5",

		.parent_names = (const char *[]){"dsi1pll_shadow_pll_out_div"},

		.num_parents = 1,

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi1pll_shadow_post_vco_div = {

	.div = 4,

	.mult = 1,
@@ -2160,6 +2189,18 @@ static struct clk_fixed_factor dsi0pll_cphy_byteclk_src = { 
	},

};



static struct clk_fixed_factor dsi0pll_shadow_cphy_byteclk_src = {

	.div = 7,

	.mult = 1,

	.hw.init = &(struct clk_init_data){

		.name = "dsi0pll_shadow_cphy_byteclk_src",

		.parent_names = (const char *[]){"dsi0pll_shadow_bitclk_src"},

		.num_parents = 1,

		.flags = (CLK_SET_RATE_PARENT),

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi1pll_cphy_byteclk_src = {

	.div = 7,

	.mult = 1,
@@ -2172,6 +2213,18 @@ static struct clk_fixed_factor dsi1pll_cphy_byteclk_src = { 
	},

};



static struct clk_fixed_factor dsi1pll_shadow_cphy_byteclk_src = {

	.div = 7,

	.mult = 1,

	.hw.init = &(struct clk_init_data){

		.name = "dsi1pll_cphy_shadow_byteclk_src",

		.parent_names = (const char *[]){"dsi1pll_shadow_bitclk_src"},

		.num_parents = 1,

		.flags = (CLK_SET_RATE_PARENT),

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi1pll_shadow_byteclk_src = {

	.div = 8,

	.mult = 1,
@@ -2236,8 +2289,9 @@ static struct clk_regmap_mux dsi0pll_byteclk_mux = { 
			.name = "dsi0_phy_pll_out_byteclk",

			.parent_names = (const char *[]){"dsi0pll_byteclk_src",

				"dsi0pll_shadow_byteclk_src",

				"dsi0pll_cphy_byteclk_src"},

			.num_parents = 3,

				"dsi0pll_cphy_byteclk_src",

				"dsi0pll_shadow_cphy_byteclk_src"},

			.num_parents = 4,

			.flags = (CLK_SET_RATE_PARENT |

					CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,
@@ -2253,8 +2307,9 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = { 
			.name = "dsi1_phy_pll_out_byteclk",

			.parent_names = (const char *[]){"dsi1pll_byteclk_src",

				"dsi1pll_shadow_byteclk_src",

				"dsi1pll_cphy_byteclk_src"},

			.num_parents = 3,

				"dsi1pll_cphy_byteclk_src",

				"dsi1pll_shadow_cphy_byteclk_src"},

			.num_parents = 4,

			.flags = (CLK_SET_RATE_PARENT |

					CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,
@@ -2308,6 +2363,22 @@ static struct clk_regmap_mux dsi0pll_cphy_pclk_src_mux = { 
	},

};



static struct clk_regmap_mux dsi0pll_shadow_cphy_pclk_src_mux = {

	.reg = PHY_CMN_CLK_CFG1,

	.shift = 0,

	.width = 2,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_shadow_cphy_pclk_src_mux",

			.parent_names =

			(const char *[]){

				"dsi0pll_shadow_post_vco_div3_5"},

			.num_parents = 1,

			.ops = &clk_regmap_mux_closest_ops,

		},

	},

};



static struct clk_regmap_mux dsi1pll_pclk_src_mux = {

	.reg = PHY_CMN_CLK_CFG1,

	.shift = 0,
@@ -2354,6 +2425,22 @@ static struct clk_regmap_mux dsi1pll_cphy_pclk_src_mux = { 
	},

};



static struct clk_regmap_mux dsi1pll_shadow_cphy_pclk_src_mux = {

	.reg = PHY_CMN_CLK_CFG1,

	.shift = 0,

	.width = 2,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_shadow_cphy_pclk_src_mux",

			.parent_names =

			(const char *[]){

				"dsi1pll_shadow_post_vco_div3_5"},

			.num_parents = 1,

			.ops = &clk_regmap_mux_closest_ops,

		},

	},

};



static struct clk_regmap_div dsi0pll_pclk_src = {

	.shift = 0,

	.width = 4,
@@ -2402,6 +2489,22 @@ static struct clk_regmap_div dsi0pll_cphy_pclk_src = { 
	},

};



static struct clk_regmap_div dsi0pll_shadow_cphy_pclk_src = {

	.shift = 0,

	.width = 4,

	.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_shadow_cphy_pclk_src",

			.parent_names = (const char *[]){

				"dsi0pll_shadow_cphy_pclk_src_mux"},

			.num_parents = 1,

			.flags = (CLK_SET_RATE_PARENT),

			.ops = &clk_regmap_div_ops,

		},

	},

};



static struct clk_regmap_div dsi1pll_pclk_src = {

	.shift = 0,

	.width = 4,
@@ -2450,6 +2553,22 @@ static struct clk_regmap_div dsi1pll_cphy_pclk_src = { 
	},

};



static struct clk_regmap_div dsi1pll_shadow_cphy_pclk_src = {

	.shift = 0,

	.width = 4,

	.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_shadow_cphy_pclk_src",

			.parent_names = (const char *[]){

				"dsi1pll_shadow_cphy_pclk_src_mux"},

			.num_parents = 1,

			.flags = (CLK_SET_RATE_PARENT),

			.ops = &clk_regmap_div_ops,

		},

	},

};



static struct clk_regmap_mux dsi0pll_pclk_mux = {

	.shift = 0,

	.width = 1,
@@ -2458,8 +2577,9 @@ static struct clk_regmap_mux dsi0pll_pclk_mux = { 
			.name = "dsi0_phy_pll_out_dsiclk",

			.parent_names = (const char *[]){"dsi0pll_pclk_src",

				"dsi0pll_shadow_pclk_src",

				"dsi0pll_cphy_pclk_src"},

			.num_parents = 3,

				"dsi0pll_cphy_pclk_src",

				"dsi0pll_shadow_cphy_pclk_src"},

			.num_parents = 4,

			.flags = (CLK_SET_RATE_PARENT |

					CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,
@@ -2475,8 +2595,9 @@ static struct clk_regmap_mux dsi1pll_pclk_mux = { 
			.name = "dsi1_phy_pll_out_dsiclk",

			.parent_names = (const char *[]){"dsi1pll_pclk_src",

				"dsi1pll_shadow_pclk_src",

				"dsi1pll_cphy_pclk_src"},

			.num_parents = 3,

				"dsi1pll_cphy_pclk_src",

				"dsi1pll_shadow_cphy_pclk_src"},

			.num_parents = 4,

			.flags = (CLK_SET_RATE_PARENT |

					CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,
@@ -2503,10 +2624,15 @@ static struct clk_hw *mdss_dsi_pllcc_7nm[] = { 
	[SHADOW_PLL_OUT_DIV_0_CLK] = &dsi0pll_shadow_pll_out_div.clkr.hw,

	[SHADOW_BITCLK_SRC_0_CLK] = &dsi0pll_shadow_bitclk_src.clkr.hw,

	[SHADOW_BYTECLK_SRC_0_CLK] = &dsi0pll_shadow_byteclk_src.hw,

	[SHADOW_CPHY_BYTECLK_SRC_0_CLK] = &dsi0pll_shadow_cphy_byteclk_src.hw,

	[SHADOW_POST_BIT_DIV_0_CLK] = &dsi0pll_shadow_post_bit_div.hw,

	[SHADOW_POST_VCO_DIV_0_CLK] = &dsi0pll_shadow_post_vco_div.hw,

	[SHADOW_POST_VCO_DIV3_5_0_CLK] = &dsi0pll_shadow_post_vco_div3_5.hw,

	[SHADOW_PCLK_SRC_MUX_0_CLK] = &dsi0pll_shadow_pclk_src_mux.clkr.hw,

	[SHADOW_PCLK_SRC_0_CLK] = &dsi0pll_shadow_pclk_src.clkr.hw,

	[SHADOW_CPHY_PCLK_SRC_MUX_0_CLK] =

			&dsi0pll_shadow_cphy_pclk_src_mux.clkr.hw,

	[SHADOW_CPHY_PCLK_SRC_0_CLK] = &dsi0pll_shadow_cphy_pclk_src.clkr.hw,

	[VCO_CLK_1] = &dsi1pll_vco_clk.hw,

	[PLL_OUT_DIV_1_CLK] = &dsi1pll_pll_out_div.clkr.hw,

	[BITCLK_SRC_1_CLK] = &dsi1pll_bitclk_src.clkr.hw,
@@ -2525,10 +2651,15 @@ static struct clk_hw *mdss_dsi_pllcc_7nm[] = { 
	[SHADOW_PLL_OUT_DIV_1_CLK] = &dsi1pll_shadow_pll_out_div.clkr.hw,

	[SHADOW_BITCLK_SRC_1_CLK] = &dsi1pll_shadow_bitclk_src.clkr.hw,

	[SHADOW_BYTECLK_SRC_1_CLK] = &dsi1pll_shadow_byteclk_src.hw,

	[SHADOW_CPHY_BYTECLK_SRC_1_CLK] = &dsi1pll_shadow_cphy_byteclk_src.hw,

	[SHADOW_POST_BIT_DIV_1_CLK] = &dsi1pll_shadow_post_bit_div.hw,

	[SHADOW_POST_VCO_DIV_1_CLK] = &dsi1pll_shadow_post_vco_div.hw,

	[SHADOW_POST_VCO_DIV3_5_1_CLK] = &dsi1pll_shadow_post_vco_div3_5.hw,

	[SHADOW_PCLK_SRC_MUX_1_CLK] = &dsi1pll_shadow_pclk_src_mux.clkr.hw,

	[SHADOW_PCLK_SRC_1_CLK] = &dsi1pll_shadow_pclk_src.clkr.hw,

	[SHADOW_CPHY_PCLK_SRC_MUX_1_CLK] =

			&dsi1pll_shadow_cphy_pclk_src_mux.clkr.hw,

	[SHADOW_CPHY_PCLK_SRC_1_CLK] = &dsi1pll_shadow_cphy_pclk_src.clkr.hw,

};



int dsi_pll_clock_register_7nm(struct platform_device *pdev,
@@ -2587,6 +2718,7 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev, 
		dsi0pll_pclk_src.clkr.regmap = rmap;

		dsi0pll_cphy_pclk_src.clkr.regmap = rmap;

		dsi0pll_shadow_pclk_src.clkr.regmap = rmap;

		dsi0pll_shadow_cphy_pclk_src.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_7nm_config);
@@ -2600,6 +2732,7 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev, 
					&cphy_pclk_src_mux_regmap_bus,

					pll_res, &dsi_pll_7nm_config);

		dsi0pll_cphy_pclk_src_mux.clkr.regmap = rmap;

		dsi0pll_shadow_cphy_pclk_src_mux.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_7nm_config);
@@ -2615,7 +2748,7 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev, 
			dsi0pll_shadow_vco_clk.max_rate = 5000000000;

		}



		for (i = VCO_CLK_0; i <= CPHY_PCLK_SRC_0_CLK; i++) {

		for (i = VCO_CLK_0; i <= SHADOW_CPHY_PCLK_SRC_0_CLK; i++) {

			clk = devm_clk_register(&pdev->dev,

						mdss_dsi_pllcc_7nm[i]);

			if (IS_ERR(clk)) {
@@ -2646,6 +2779,7 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev, 
		dsi1pll_pclk_src.clkr.regmap = rmap;

		dsi1pll_cphy_pclk_src.clkr.regmap = rmap;

		dsi1pll_shadow_pclk_src.clkr.regmap = rmap;

		dsi1pll_shadow_cphy_pclk_src.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_7nm_config);
@@ -2659,6 +2793,7 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev, 
					&cphy_pclk_src_mux_regmap_bus,

					pll_res, &dsi_pll_7nm_config);

		dsi1pll_cphy_pclk_src_mux.clkr.regmap = rmap;

		dsi1pll_shadow_cphy_pclk_src_mux.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_7nm_config);
@@ -2673,7 +2808,7 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev, 
			dsi1pll_shadow_vco_clk.max_rate = 5000000000;

		}



		for (i = VCO_CLK_1; i <= CPHY_PCLK_SRC_1_CLK; i++) {

		for (i = VCO_CLK_1; i <= SHADOW_CPHY_PCLK_SRC_1_CLK; i++) {

			clk = devm_clk_register(&pdev->dev,

						mdss_dsi_pllcc_7nm[i]);

			if (IS_ERR(clk)) {