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Commit b0ebde39 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: L3 cache remapping is part of context switching 



Move the i915_gem_l3_remap function such that it next to the context
switching, which is where we perform the L3 remap.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461833819-3991-8-git-send-email-chris@chris-wilson.co.uk
parent b2e862d0

drivers/gpu/drm/i915/i915_gem.c

+0 −31
Original line number Diff line number Diff line
@@ -4738,37 +4738,6 @@ i915_gem_suspend(struct drm_device *dev) 
	return ret;

}



int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)

{

	struct intel_engine_cs *engine = req->engine;

	struct drm_device *dev = engine->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 *remap_info = dev_priv->l3_parity.remap_info[slice];

	int i, ret;



	if (!HAS_L3_DPF(dev) || !remap_info)

		return 0;



	ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);

	if (ret)

		return ret;



	/*

	 * Note: We do not worry about the concurrent register cacheline hang

	 * here because no other code should access these registers other than

	 * at initialization time.

	 */

	for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {

		intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));

		intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i));

		intel_ring_emit(engine, remap_info[i]);

	}



	intel_ring_advance(engine);



	return ret;

}



void i915_gem_init_swizzling(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

drivers/gpu/drm/i915/i915_gem_context.c

+31 −0
Original line number Diff line number Diff line
@@ -601,6 +601,37 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) 
	return ret;

}



int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)

{

	struct intel_engine_cs *engine = req->engine;

	struct drm_device *dev = engine->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 *remap_info = dev_priv->l3_parity.remap_info[slice];

	int i, ret;



	if (!HAS_L3_DPF(dev) || !remap_info)

		return 0;



	ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);

	if (ret)

		return ret;



	/*

	 * Note: We do not worry about the concurrent register cacheline hang

	 * here because no other code should access these registers other than

	 * at initialization time.

	 */

	for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {

		intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));

		intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i));

		intel_ring_emit(engine, remap_info[i]);

	}



	intel_ring_advance(engine);



	return ret;

}



static inline bool skip_rcs_switch(struct intel_engine_cs *engine,

				   struct intel_context *to)

{