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Commit b0dd6887 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/dsi: rename intel_dsi_exec_vbt_sequence to intel_dsi_vbt_exec_sequence 



Use the prefix intel_dsi_vbt for all the DSI VBT functions. No
functional changes.

Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Reviewed-by: default avatarBob Paauwe <bob.j.paauwe@intel.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/0a05abca364f3bc7f9caf90c9bd3a68eef5f222f.1488810382.git.jani.nikula@intel.com
parent 3f751d65

drivers/gpu/drm/i915/intel_dsi.c

+12 −12
Original line number Diff line number Diff line
@@ -806,38 +806,38 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, 
	/* Power on, try both CRC pmic gpio and VBT */

	if (intel_dsi->gpio_panel)

		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);

	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);

	intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);



	/* Deassert reset */

	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);



	/* Put device in ready state (LP-11) */

	intel_dsi_device_ready(encoder);



	/* Send initialization commands in LP mode */

	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);



	/* Enable port in pre-enable phase itself because as per hw team

	 * recommendation, port should be enabled befor plane & pipe */

	if (is_cmd_mode(intel_dsi)) {

		for_each_dsi_port(port, intel_dsi->ports)

			I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);

		intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);

		intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);

		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);

		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);

	} else {

		msleep(20); /* XXX */

		for_each_dsi_port(port, intel_dsi->ports)

			dpi_send_cmd(intel_dsi, TURN_ON, false, port);

		intel_dsi_msleep(intel_dsi, 100);



		intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);

		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);



		intel_dsi_port_enable(encoder);

	}



	intel_panel_enable_backlight(intel_dsi->attached_connector);

	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);

}



static void intel_dsi_enable_nop(struct intel_encoder *encoder,
@@ -863,7 +863,7 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder, 


	DRM_DEBUG_KMS("\n");



	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);

	intel_panel_disable_backlight(intel_dsi->attached_connector);



	/*
@@ -925,8 +925,8 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, 
	 * some next enable sequence send turn on packet error is observed

	 */

	if (is_cmd_mode(intel_dsi))

		intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);

	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);

		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);



	/* Transition to LP-00 */

	intel_dsi_clear_device_ready(encoder);
@@ -953,11 +953,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, 
	}



	/* Assert reset */

	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);



	/* Power off, try both CRC pmic gpio and VBT */

	intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);

	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);

	if (intel_dsi->gpio_panel)

		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);

drivers/gpu/drm/i915/intel_dsi.h

+2 −3
Original line number Diff line number Diff line
@@ -131,9 +131,6 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) 


void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port);



void intel_dsi_exec_vbt_sequence(struct intel_dsi *intel_dsi,

				 enum mipi_seq seq_id);



bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);

int intel_compute_dsi_pll(struct intel_encoder *encoder,

			  struct intel_crtc_state *config);
@@ -147,6 +144,8 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, 


bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);

int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);

void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,

				 enum mipi_seq seq_id);

enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);



#endif /* _INTEL_DSI_H */

drivers/gpu/drm/i915/intel_dsi_panel_vbt.c

+1 −1
Original line number Diff line number Diff line
@@ -415,7 +415,7 @@ static const char *sequence_name(enum mipi_seq seq_id) 
		return "(unknown)";

}



void intel_dsi_exec_vbt_sequence(struct intel_dsi *intel_dsi,

void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,

				 enum mipi_seq seq_id)

{

	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);