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Commit b0cd324f authored by Jani Nikula's avatar Jani Nikula Committed by Daniel Vetter
Browse files

drm/i915: don't save/restore backlight hist ctl registers 



This is not used within the driver, and merely saving/restoring these
registers isn't going to do any good anyway. In fact, it's possible it's
actively harmful. Any code enabling the feature should handle this
completely in the regular platform specific enable/disable backlight
functions.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f7faa1ef

drivers/gpu/drm/i915/i915_drv.h

+0 −1
Original line number Diff line number Diff line
@@ -799,7 +799,6 @@ struct i915_suspend_saved_registers { 
	u32 saveBLC_HIST_CTL;

	u32 saveBLC_PWM_CTL;

	u32 saveBLC_PWM_CTL2;

	u32 saveBLC_HIST_CTL_B;

	u32 saveBLC_CPU_PWM_CTL;

	u32 saveBLC_CPU_PWM_CTL2;

	u32 saveFPB0;

drivers/gpu/drm/i915/i915_suspend.c

+2 −14
Original line number Diff line number Diff line
@@ -207,14 +207,8 @@ static void i915_save_display(struct drm_device *dev) 
		dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);

		if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))

			dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);

	} else if (IS_VALLEYVIEW(dev)) {

		dev_priv->regfile.saveBLC_HIST_CTL =

			I915_READ(VLV_BLC_HIST_CTL(PIPE_A));

		dev_priv->regfile.saveBLC_HIST_CTL_B =

			I915_READ(VLV_BLC_HIST_CTL(PIPE_B));

	} else {

	} else if (!IS_VALLEYVIEW(dev)) {

		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);

		dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);

		if (IS_MOBILE(dev) && !IS_I830(dev))

			dev_priv->regfile.saveLVDS = I915_READ(LVDS);

	}
@@ -262,13 +256,7 @@ static void i915_restore_display(struct drm_device *dev) 
		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);

		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);

		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);

	} else if (IS_VALLEYVIEW(dev)) {

		I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A),

			   dev_priv->regfile.saveBLC_HIST_CTL);

		I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),

			   dev_priv->regfile.saveBLC_HIST_CTL);

	} else {

		I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);

	} else if (!IS_VALLEYVIEW(dev)) {

		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);

		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);

		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);

drivers/gpu/drm/i915/i915_ums.c

+2 −0
Original line number Diff line number Diff line
@@ -290,6 +290,7 @@ void i915_save_display_reg(struct drm_device *dev) 
		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);

		if (INTEL_INFO(dev)->gen >= 4)

			dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);

		dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);

	}



	return;
@@ -319,6 +320,7 @@ void i915_restore_display_reg(struct drm_device *dev) 
		if (INTEL_INFO(dev)->gen >= 4)

			I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);

		I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);

		I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);

	}



	/* Panel fitter */