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Commit b0a852c4 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add UFS ICE HW controlled clock for lito"

parents b13752ea ed688a6e

qcom/lito.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -1811,6 +1811,7 @@ 
			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"core_clk_ice_hw_ctl",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",
@@ -1821,6 +1822,7 @@ 
			<&gcc GCC_UFS_PHY_AHB_CLK>,

			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
@@ -1831,6 +1833,7 @@ 
			<0 0>,

			<37500000 150000000>,

			<75000000 300000000>,

			<75000000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,