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Commit b095cd0a authored by Jesse Barnes's avatar Jesse Barnes
Browse files

drm/i915: set GFX_MODE to pre-Ivybridge default value even on Ivybridge 



Prior to Ivybridge, the GFX_MODE would default to 0x800, meaning that
MI_FLUSH would flush the TLBs in addition to the rest of the caches
indicated in the MI_FLUSH command.  However starting with Ivybridge, the
register defaults to 0x2800 out of reset, meaning that to invalidate the
TLB we need to use PIPE_CONTROL.  Since we're not doing that yet, go
back to the old default so things work.

v2: don't forget to actually *clear* the new bit

Reviewed-by: default avatarEric Anholt <eric@anholt.net>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Tested-by: default avatarKenneth Graunke <kenneth@whitecape.org>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent 4e634389

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -375,6 +375,7 @@ 
# define MI_FLUSH_ENABLE				(1 << 11)



#define GFX_MODE	0x02520

#define GFX_MODE_GEN7	0x0229c

#define   GFX_RUN_LIST_ENABLE		(1<<15)

#define   GFX_TLB_INVALIDATE_ALWAYS	(1<<13)

#define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
@@ -382,6 +383,9 @@ 
#define   GFX_PSMI_GRANULARITY		(1<<10)

#define   GFX_PPGTT_ENABLE		(1<<9)



#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))

#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))



#define SCPD0		0x0209c /* 915+ only */

#define IER		0x020a0

#define IIR		0x020a4

drivers/gpu/drm/i915/intel_ringbuffer.c

+4 −0
Original line number Diff line number Diff line
@@ -290,6 +290,10 @@ static int init_render_ring(struct intel_ring_buffer *ring) 
		if (IS_GEN6(dev) || IS_GEN7(dev))

			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;

		I915_WRITE(MI_MODE, mode);

		if (IS_GEN7(dev))

			I915_WRITE(GFX_MODE_GEN7,

				   GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |

				   GFX_MODE_ENABLE(GFX_REPLAY_MODE));

	}



	if (INTEL_INFO(dev)->gen >= 6) {