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Commit b039d6d0 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2016-01-24' of git://anongit.freedesktop.org/drm-intel into drm-next 

- support for v3 vbt dsi blocks (Jani)
- improve mmio debug checks (Mika Kuoppala)
- reorg the ddi port translation table entries and related code (Ville)
- reorg gen8 interrupt handling for future platforms (Tvrtko)
- refactor tile width/height computations for framebuffers (Ville)
- kerneldoc integration for intel_pm.c (Jani)
- move default context from engines to device-global dev_priv (Dave Gordon)
- make seqno/irq ordering coherent with execlist (Chris)
- decouple internal engine number from UABI (Chris&Tvrtko)
- tons of small fixes all over, as usual

* tag 'drm-intel-next-2016-01-24' of git://anongit.freedesktop.org/drm-intel: (148 commits)
  drm/i915: Update DRIVER_DATE to 20160124
  drm/i915: Seal busy-ioctl uABI and prevent leaking of internal ids
  drm/i915: Decouple execbuf uAPI from internal implementation
  drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists
  drm/i915: Limit the auto arming of mmio debugs on vlv/chv
  drm/i915: Tune down "GT register while GT waking disabled" message
  drm/i915: tidy up a few leftovers
  drm/i915: abolish separate per-ring default_context pointers
  drm/i915: simplify allocation of driver-internal requests
  drm/i915: Fix NULL plane->fb oops on SKL
  drm/i915: Do not put big intel_crtc_state on the stack
  Revert "drm/i915: Add two-stage ILK-style watermark programming (v10)"
  drm/i915: add DOC: headline to RC6 kernel-doc
  drm/i915: turn some bogus kernel-doc comments to normal comments
  drm/i915/sdvo: revert bogus kernel-doc comments to normal comments
  drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
  drm/i915: Demote user facing DMC firmware load failure message
  drm/i915: use hlist_for_each_entry
  drm/i915: skl_update_scaler() wants a rotation bitmask instead of bit number
  drm/i915: Don't reject primary plane windowing with color keying enabled on SKL+
  ...
parents 388f7b1d 947eaebc

Documentation/DocBook/gpu.tmpl

+6 −0
Original line number Diff line number Diff line
@@ -3319,6 +3319,12 @@ int num_ioctls;</synopsis> 
!Pdrivers/gpu/drm/i915/intel_csr.c csr support for dmc

!Idrivers/gpu/drm/i915/intel_csr.c

      </sect2>

      <sect2>

	<title>Video BIOS Table (VBT)</title>

!Pdrivers/gpu/drm/i915/intel_bios.c Video BIOS Table (VBT)

!Idrivers/gpu/drm/i915/intel_bios.c

!Idrivers/gpu/drm/i915/intel_bios.h

      </sect2>

    </sect1>



    <sect1>

drivers/gpu/drm/i915/i915_debugfs.c

+33 −23
Original line number Diff line number Diff line
@@ -1331,7 +1331,8 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused) 
	struct intel_engine_cs *ring;

	u64 acthd[I915_NUM_RINGS];

	u32 seqno[I915_NUM_RINGS];

	int i;

	u32 instdone[I915_NUM_INSTDONE_REG];

	int i, j;



	if (!i915.enable_hangcheck) {

		seq_printf(m, "Hangcheck disabled\n");
@@ -1345,6 +1346,8 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused) 
		acthd[i] = intel_ring_get_active_head(ring);

	}



	i915_get_extra_instdone(dev, instdone);



	intel_runtime_pm_put(dev_priv);



	if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
@@ -1365,6 +1368,21 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused) 
			   (long long)ring->hangcheck.max_acthd);

		seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);

		seq_printf(m, "\taction = %d\n", ring->hangcheck.action);



		if (ring->id == RCS) {

			seq_puts(m, "\tinstdone read =");



			for (j = 0; j < I915_NUM_INSTDONE_REG; j++)

				seq_printf(m, " 0x%08x", instdone[j]);



			seq_puts(m, "\n\tinstdone accu =");



			for (j = 0; j < I915_NUM_INSTDONE_REG; j++)

				seq_printf(m, " 0x%08x",

					   ring->hangcheck.instdone[j]);



			seq_puts(m, "\n");

		}

	}



	return 0;
@@ -1942,11 +1960,8 @@ static int i915_context_status(struct seq_file *m, void *unused) 


		seq_puts(m, "HW context ");

		describe_ctx(m, ctx);

		for_each_ring(ring, dev_priv, i) {

			if (ring->default_context == ctx)

				seq_printf(m, "(default context %s) ",

					   ring->name);

		}

		if (ctx == dev_priv->kernel_context)

			seq_printf(m, "(kernel context) ");



		if (i915.enable_execlists) {

			seq_putc(m, '\n');
@@ -1976,12 +1991,13 @@ static int i915_context_status(struct seq_file *m, void *unused) 
}



static void i915_dump_lrc_obj(struct seq_file *m,

			      struct intel_engine_cs *ring,

			      struct drm_i915_gem_object *ctx_obj)

			      struct intel_context *ctx,

			      struct intel_engine_cs *ring)

{

	struct page *page;

	uint32_t *reg_state;

	int j;

	struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;

	unsigned long ggtt_offset = 0;



	if (ctx_obj == NULL) {
@@ -1991,7 +2007,7 @@ static void i915_dump_lrc_obj(struct seq_file *m, 
	}



	seq_printf(m, "CONTEXT: %s %u\n", ring->name,

		   intel_execlists_ctx_id(ctx_obj));

		   intel_execlists_ctx_id(ctx, ring));



	if (!i915_gem_obj_ggtt_bound(ctx_obj))

		seq_puts(m, "\tNot bound in GGTT\n");
@@ -2037,13 +2053,10 @@ static int i915_dump_lrc(struct seq_file *m, void *unused) 
	if (ret)

		return ret;



	list_for_each_entry(ctx, &dev_priv->context_list, link) {

		for_each_ring(ring, dev_priv, i) {

			if (ring->default_context != ctx)

				i915_dump_lrc_obj(m, ring,

						  ctx->engine[i].state);

		}

	}

	list_for_each_entry(ctx, &dev_priv->context_list, link)

		if (ctx != dev_priv->kernel_context)

			for_each_ring(ring, dev_priv, i)

				i915_dump_lrc_obj(m, ctx, ring);



	mutex_unlock(&dev->struct_mutex);
@@ -2092,13 +2105,13 @@ static int i915_execlists(struct seq_file *m, void *data) 
		seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);



		read_pointer = ring->next_context_status_buffer;

		write_pointer = status_pointer & 0x07;

		write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);

		if (read_pointer > write_pointer)

			write_pointer += 6;

			write_pointer += GEN8_CSB_ENTRIES;

		seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",

			   read_pointer, write_pointer);



		for (i = 0; i < 6; i++) {

		for (i = 0; i < GEN8_CSB_ENTRIES; i++) {

			status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));

			ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
@@ -2115,11 +2128,8 @@ static int i915_execlists(struct seq_file *m, void *data) 


		seq_printf(m, "\t%d requests in queue\n", count);

		if (head_req) {

			struct drm_i915_gem_object *ctx_obj;



			ctx_obj = head_req->ctx->engine[ring_id].state;

			seq_printf(m, "\tHead request id: %u\n",

				   intel_execlists_ctx_id(ctx_obj));

				   intel_execlists_ctx_id(head_req->ctx, ring));

			seq_printf(m, "\tHead request tail: %u\n",

				   head_req->tail);

		}

drivers/gpu/drm/i915/i915_drv.c

+10 −5
Original line number Diff line number Diff line
@@ -1079,7 +1079,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv) 
	 */

	broxton_init_cdclk(dev);

	broxton_ddi_phy_init(dev);

	intel_prepare_ddi(dev);



	return 0;

}
@@ -1338,7 +1337,7 @@ static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, 
		return 0;



	DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",

			wait_for_on ? "on" : "off",

		      onoff(wait_for_on),

		      I915_READ(VLV_GTLC_PW_STATUS));



	/*
@@ -1348,7 +1347,7 @@ static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, 
	err = wait_for(COND, 3);

	if (err)

		DRM_ERROR("timeout waiting for GT wells to go %s\n",

			  wait_for_on ? "on" : "off");

			  onoff(wait_for_on));



	return err;

#undef COND
@@ -1359,7 +1358,7 @@ static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) 
	if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))

		return;



	DRM_ERROR("GT register access while GT waking disabled\n");

	DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");

	I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);

}
@@ -1503,6 +1502,10 @@ static int intel_runtime_suspend(struct device *device) 


	enable_rpm_wakeref_asserts(dev_priv);

	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));



	if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))

		DRM_ERROR("Unclaimed access detected prior to suspending\n");



	dev_priv->pm.suspended = true;



	/*
@@ -1551,6 +1554,8 @@ static int intel_runtime_resume(struct device *device) 


	intel_opregion_notify_adapter(dev, PCI_D0);

	dev_priv->pm.suspended = false;

	if (intel_uncore_unclaimed_mmio(dev_priv))

		DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");



	intel_guc_resume(dev);

drivers/gpu/drm/i915/i915_drv.h

+41 −67
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#include <uapi/drm/drm_fourcc.h>



#include <drm/drmP.h>

#include "i915_params.h"

#include "i915_reg.h"

#include "intel_bios.h"

#include "intel_ringbuffer.h"
@@ -58,7 +59,7 @@ 


#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20151218"

#define DRIVER_DATE		"20160124"



#undef WARN_ON

/* Many gcc seem to no see through this and fall over :( */
@@ -69,11 +70,11 @@ 
		BUILD_BUG_ON(__i915_warn_cond); \

	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })

#else

#define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )

#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")

#endif



#undef WARN_ON_ONCE

#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )

#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")



#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \

			     (long) (x), __func__);
@@ -87,31 +88,25 @@ 
 */

#define I915_STATE_WARN(condition, format...) ({			\

	int __ret_warn_on = !!(condition);				\

	if (unlikely(__ret_warn_on)) {					\

		if (i915.verbose_state_checks)				\

			WARN(1, format);				\

		else 							\

	if (unlikely(__ret_warn_on))					\

		if (!WARN(i915.verbose_state_checks, format))		\

			DRM_ERROR(format);				\

	}								\

	unlikely(__ret_warn_on);					\

})



#define I915_STATE_WARN_ON(condition) ({				\

	int __ret_warn_on = !!(condition);				\

	if (unlikely(__ret_warn_on)) {					\

		if (i915.verbose_state_checks)				\

			WARN(1, "WARN_ON(" #condition ")\n");		\

		else 							\

			DRM_ERROR("WARN_ON(" #condition ")\n");		\

	}								\

	unlikely(__ret_warn_on);					\

})

#define I915_STATE_WARN_ON(x)						\

	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")



static inline const char *yesno(bool v)

{

	return v ? "yes" : "no";

}



static inline const char *onoff(bool v)

{

	return v ? "on" : "off";

}



enum pipe {

	INVALID_PIPE = -1,

	PIPE_A = 0,
@@ -339,7 +334,7 @@ struct drm_i915_file_private { 
		unsigned boosts;

	} rps;



	struct intel_engine_cs *bsd_ring;

	unsigned int bsd_ring;

};



enum intel_dpll_id {
@@ -633,6 +628,7 @@ struct drm_i915_display_funcs { 
			  struct dpll *best_clock);

	int (*compute_pipe_wm)(struct intel_crtc *crtc,

			       struct drm_atomic_state *state);

	void (*program_watermarks)(struct intel_crtc_state *cstate);

	void (*update_wm)(struct drm_crtc *crtc);

	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);

	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
@@ -657,9 +653,6 @@ struct drm_i915_display_funcs { 
			  struct drm_i915_gem_object *obj,

			  struct drm_i915_gem_request *req,

			  uint32_t flags);

	void (*update_primary_plane)(struct drm_crtc *crtc,

				     struct drm_framebuffer *fb,

				     int x, int y);

	void (*hpd_irq_setup)(struct drm_device *dev);

	/* clock updates for mode set */

	/* cursor updates */
@@ -726,6 +719,8 @@ struct intel_uncore { 
		i915_reg_t reg_post;

		u32 val_reset;

	} fw_domain[FW_DOMAIN_ID_COUNT];



	int unclaimed_mmio_check;

};



/* Iterate over initialised fw domains */
@@ -889,6 +884,9 @@ struct intel_context { 
		struct drm_i915_gem_object *state;

		struct intel_ringbuffer *ringbuf;

		int pin_count;

		struct i915_vma *lrc_vma;

		u64 lrc_desc;

		uint32_t *lrc_reg_state;

	} engine[I915_NUM_RINGS];



	struct list_head link;
@@ -1301,7 +1299,7 @@ struct i915_gem_mm { 
	bool busy;



	/* the indicator for dispatch video commands on two BSD rings */

	int bsd_ring_dispatch_index;

	unsigned int bsd_ring_dispatch_index;



	/** Bit 6 swizzling required for X tiling */

	uint32_t bit_6_swizzle_x;
@@ -1487,7 +1485,7 @@ struct intel_vbt_data { 
		u8 seq_version;

		u32 size;

		u8 *data;

		u8 *sequence[MIPI_SEQ_MAX];

		const u8 *sequence[MIPI_SEQ_MAX];

	} dsi;



	int crt_ddc_pin;
@@ -1784,7 +1782,7 @@ struct drm_i915_private { 


	unsigned int fsb_freq, mem_freq, is_ddr3;

	unsigned int skl_boot_cdclk;

	unsigned int cdclk_freq, max_cdclk_freq;

	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;

	unsigned int max_dotclk_freq;

	unsigned int hpll_freq;

	unsigned int czclk_freq;
@@ -1829,8 +1827,13 @@ struct drm_i915_private { 
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];

#endif



	/* dpll and cdclk state is protected by connection_mutex */

	int num_shared_dpll;

	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];



	unsigned int active_crtcs;

	unsigned int min_pixclk[I915_MAX_PIPES];



	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];



	struct i915_workarounds workarounds;
@@ -1945,6 +1948,8 @@ struct drm_i915_private { 
		void (*stop_ring)(struct intel_engine_cs *ring);

	} gt;



	struct intel_context *kernel_context;



	bool edp_low_vswing;



	/* perform PHY state sanity checks? */
@@ -2265,9 +2270,9 @@ struct drm_i915_gem_request { 


};



int i915_gem_request_alloc(struct intel_engine_cs *ring,

			   struct intel_context *ctx,

			   struct drm_i915_gem_request **req_out);

struct drm_i915_gem_request * __must_check

i915_gem_request_alloc(struct intel_engine_cs *engine,

		       struct intel_context *ctx);

void i915_gem_request_cancel(struct drm_i915_gem_request *req);

void i915_gem_request_free(struct kref *req_ref);

int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
@@ -2576,6 +2581,11 @@ struct drm_i915_cmd_table { 


/* Early gen2 have a totally busted CS tlb and require pinned batches. */

#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))



/* WaRsDisableCoarsePowerGating:skl,bxt */

#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \

						 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \

						  IS_SKL_REVID(dev, 0, SKL_REVID_F0)))

/*

 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts

 * even when in MSI mode. This results in spurious interrupt warnings if the
@@ -2665,43 +2675,6 @@ extern int i915_max_ioctl; 
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);

extern int i915_resume_switcheroo(struct drm_device *dev);



/* i915_params.c */

struct i915_params {

	int modeset;

	int panel_ignore_lid;

	int semaphores;

	int lvds_channel_mode;

	int panel_use_ssc;

	int vbt_sdvo_panel_type;

	int enable_rc6;

	int enable_dc;

	int enable_fbc;

	int enable_ppgtt;

	int enable_execlists;

	int enable_psr;

	unsigned int preliminary_hw_support;

	int disable_power_well;

	int enable_ips;

	int invert_brightness;

	int enable_cmd_parser;

	/* leave bools at the end to not create holes */

	bool enable_hangcheck;

	bool fastboot;

	bool prefault_disable;

	bool load_detect_test;

	bool reset;

	bool disable_display;

	bool disable_vtd_wa;

	bool enable_guc_submission;

	int guc_log_level;

	int use_mmio_flip;

	int mmio_debug;

	bool verbose_state_checks;

	bool nuclear_pageflip;

	int edp_vswing;

};

extern struct i915_params i915 __read_mostly;



/* i915_dma.c */

extern int i915_driver_load(struct drm_device *, unsigned long flags);

extern int i915_driver_unload(struct drm_device *);
@@ -2745,7 +2718,8 @@ extern void intel_uncore_sanitize(struct drm_device *dev); 
extern void intel_uncore_early_sanitize(struct drm_device *dev,

					bool restore_forcewake);

extern void intel_uncore_init(struct drm_device *dev);

extern void intel_uncore_check_errors(struct drm_device *dev);

extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);

extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);

extern void intel_uncore_fini(struct drm_device *dev);

extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);

const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);

drivers/gpu/drm/i915/i915_gem.c

+68 −27
Original line number Diff line number Diff line
@@ -1251,7 +1251,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req, 
	int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;

	DEFINE_WAIT(wait);

	unsigned long timeout_expire;

	s64 before, now;

	s64 before = 0; /* Only to silence a compiler warning. */

	int ret;



	WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
@@ -1271,14 +1271,17 @@ int __i915_wait_request(struct drm_i915_gem_request *req, 
			return -ETIME;



		timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout);



		/*

		 * Record current time in case interrupted by signal, or wedged.

		 */

		before = ktime_get_raw_ns();

	}



	if (INTEL_INFO(dev_priv)->gen >= 6)

		gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);



	/* Record current time in case interrupted by signal, or wedged */

	trace_i915_gem_request_wait_begin(req);

	before = ktime_get_raw_ns();



	/* Optimistic spin for the next jiffie before touching IRQs */

	ret = __i915_spin_request(req, state);
@@ -1343,11 +1346,10 @@ int __i915_wait_request(struct drm_i915_gem_request *req, 
	finish_wait(&ring->irq_queue, &wait);



out:

	now = ktime_get_raw_ns();

	trace_i915_gem_request_wait_end(req);



	if (timeout) {

		s64 tres = *timeout - (now - before);

		s64 tres = *timeout - (ktime_get_raw_ns() - before);



		*timeout = tres < 0 ? 0 : tres;
@@ -2677,10 +2679,8 @@ void i915_gem_request_free(struct kref *req_ref) 
		i915_gem_request_remove_from_client(req);



	if (ctx) {

		if (i915.enable_execlists) {

			if (ctx != req->ring->default_context)

		if (i915.enable_execlists && ctx != req->i915->kernel_context)

			intel_lr_context_unpin(req);

		}



		i915_gem_context_unreference(ctx);

	}
@@ -2688,7 +2688,8 @@ void i915_gem_request_free(struct kref *req_ref) 
	kmem_cache_free(req->i915->requests, req);

}



int i915_gem_request_alloc(struct intel_engine_cs *ring,

static inline int

__i915_gem_request_alloc(struct intel_engine_cs *ring,

			 struct intel_context *ctx,

			 struct drm_i915_gem_request **req_out)

{
@@ -2753,6 +2754,31 @@ int i915_gem_request_alloc(struct intel_engine_cs *ring, 
	return ret;

}



/**

 * i915_gem_request_alloc - allocate a request structure

 *

 * @engine: engine that we wish to issue the request on.

 * @ctx: context that the request will be associated with.

 *       This can be NULL if the request is not directly related to

 *       any specific user context, in which case this function will

 *       choose an appropriate context to use.

 *

 * Returns a pointer to the allocated request if successful,

 * or an error code if not.

 */

struct drm_i915_gem_request *

i915_gem_request_alloc(struct intel_engine_cs *engine,

		       struct intel_context *ctx)

{

	struct drm_i915_gem_request *req;

	int err;



	if (ctx == NULL)

		ctx = to_i915(engine->dev)->kernel_context;

	err = __i915_gem_request_alloc(engine, ctx, &req);

	return err ? ERR_PTR(err) : req;

}



void i915_gem_request_cancel(struct drm_i915_gem_request *req)

{

	intel_ring_reserved_space_cancel(req->ringbuf);
@@ -3170,9 +3196,13 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj, 
			return 0;



		if (*to_req == NULL) {

			ret = i915_gem_request_alloc(to, to->default_context, to_req);

			if (ret)

				return ret;

			struct drm_i915_gem_request *req;



			req = i915_gem_request_alloc(to, NULL);

			if (IS_ERR(req))

				return PTR_ERR(req);



			*to_req = req;

		}



		trace_i915_gem_ring_sync_to(*to_req, from, from_req);
@@ -3372,9 +3402,9 @@ int i915_gpu_idle(struct drm_device *dev) 
		if (!i915.enable_execlists) {

			struct drm_i915_gem_request *req;



			ret = i915_gem_request_alloc(ring, ring->default_context, &req);

			if (ret)

				return ret;

			req = i915_gem_request_alloc(ring, NULL);

			if (IS_ERR(req))

				return PTR_ERR(req);



			ret = i915_switch_context(req);

			if (ret) {
@@ -4328,10 +4358,20 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data, 
	if (ret)

		goto unref;



	BUILD_BUG_ON(I915_NUM_RINGS > 16);

	args->busy = obj->active << 16;

	args->busy = 0;

	if (obj->active) {

		int i;



		for (i = 0; i < I915_NUM_RINGS; i++) {

			struct drm_i915_gem_request *req;



			req = obj->last_read_req[i];

			if (req)

				args->busy |= 1 << (16 + req->ring->exec_id);

		}

		if (obj->last_write_req)

		args->busy |= obj->last_write_req->ring->id;

			args->busy |= obj->last_write_req->ring->exec_id;

	}



unref:

	drm_gem_object_unreference(&obj->base);
@@ -4832,7 +4872,7 @@ i915_gem_init_hw(struct drm_device *dev) 
	 */

	init_unused_rings(dev);



	BUG_ON(!dev_priv->ring[RCS].default_context);

	BUG_ON(!dev_priv->kernel_context);



	ret = i915_ppgtt_init_hw(dev);

	if (ret) {
@@ -4869,10 +4909,9 @@ i915_gem_init_hw(struct drm_device *dev) 
	for_each_ring(ring, dev_priv, i) {

		struct drm_i915_gem_request *req;



		WARN_ON(!ring->default_context);



		ret = i915_gem_request_alloc(ring, ring->default_context, &req);

		if (ret) {

		req = i915_gem_request_alloc(ring, NULL);

		if (IS_ERR(req)) {

			ret = PTR_ERR(req);

			i915_gem_cleanup_ringbuffer(dev);

			goto out;

		}
@@ -5112,6 +5151,8 @@ int i915_gem_open(struct drm_device *dev, struct drm_file *file) 
	spin_lock_init(&file_priv->mm.lock);

	INIT_LIST_HEAD(&file_priv->mm.request_list);



	file_priv->bsd_ring = -1;



	ret = i915_gem_context_open(dev, file);

	if (ret)

		kfree(file_priv);