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Commit b00855ae authored by Srinidhi Kasagar's avatar Srinidhi Kasagar Committed by Rafael J. Wysocki
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ACPI / LPSS: Ignore 10ms delay for Braswell 



LPSS devices in Braswell does not need the default 10ms
d3_delay imposed by PCI specification. Removing this
unnecessary delay significantly reduces the resume time
approximately upto 200ms on this platform.

Signed-off-by: default avatarSrinidhi Kasagar <srinidhi.kasagar@intel.com>
Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent c13dcf9f

drivers/acpi/acpi_lpss.c

+32 −6
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ ACPI_MODULE_NAME("acpi_lpss"); 
#define LPSS_CLK_DIVIDER		BIT(2)

#define LPSS_LTR			BIT(3)

#define LPSS_SAVE_CTX			BIT(4)

#define LPSS_NO_D3_DELAY		BIT(5)



struct lpss_private_data;
@@ -156,6 +157,10 @@ static const struct lpss_device_desc byt_pwm_dev_desc = { 
	.flags = LPSS_SAVE_CTX,

};



static const struct lpss_device_desc bsw_pwm_dev_desc = {

	.flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,

};



static const struct lpss_device_desc byt_uart_dev_desc = {

	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,

	.clk_con_id = "baudclk",
@@ -163,6 +168,14 @@ static const struct lpss_device_desc byt_uart_dev_desc = { 
	.setup = lpss_uart_setup,

};



static const struct lpss_device_desc bsw_uart_dev_desc = {

	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX

			| LPSS_NO_D3_DELAY,

	.clk_con_id = "baudclk",

	.prv_offset = 0x800,

	.setup = lpss_uart_setup,

};



static const struct lpss_device_desc byt_spi_dev_desc = {

	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,

	.prv_offset = 0x400,
@@ -178,8 +191,15 @@ static const struct lpss_device_desc byt_i2c_dev_desc = { 
	.setup = byt_i2c_setup,

};



static const struct lpss_device_desc bsw_i2c_dev_desc = {

	.flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,

	.prv_offset = 0x800,

	.setup = byt_i2c_setup,

};



static struct lpss_device_desc bsw_spi_dev_desc = {

	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,

	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX

			| LPSS_NO_D3_DELAY,

	.prv_offset = 0x400,

	.setup = lpss_deassert_reset,

};
@@ -214,11 +234,12 @@ static const struct acpi_device_id acpi_lpss_device_ids[] = { 
	{ "INT33FC", },



	/* Braswell LPSS devices */

	{ "80862288", LPSS_ADDR(byt_pwm_dev_desc) },

	{ "8086228A", LPSS_ADDR(byt_uart_dev_desc) },

	{ "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },

	{ "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },

	{ "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },

	{ "808622C1", LPSS_ADDR(byt_i2c_dev_desc) },

	{ "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },



	/* Broadwell LPSS devices */

	{ "INT3430", LPSS_ADDR(lpt_dev_desc) },

	{ "INT3431", LPSS_ADDR(lpt_dev_desc) },

	{ "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
@@ -558,9 +579,14 @@ static void acpi_lpss_restore_ctx(struct device *dev, 
	 * The following delay is needed or the subsequent write operations may

	 * fail. The LPSS devices are actually PCI devices and the PCI spec

	 * expects 10ms delay before the device can be accessed after D3 to D0

	 * transition.

	 * transition. However some platforms like BSW does not need this delay.

	 */

	msleep(10);

	unsigned int delay = 10;	/* default 10ms delay */



	if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)

		delay = 0;



	msleep(delay);



	for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {

		unsigned long offset = i * sizeof(u32);