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Commit af0ffe0a authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add PM QoS and DLL settings for scuba"

parents 383bbdba d11d7e69

qcom/scuba.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -874,6 +874,13 @@ 


		qcom,scaling-lower-bus-speed-mode = "DDR52";



		/* PM QoS */

		qcom,pm-qos-irq-type = "affine_irq";

		qcom,pm-qos-irq-latency = <43 43>;

		qcom,pm-qos-cpu-groups = <0x0f>;

		qcom,pm-qos-cmdq-latency-us = <43 43>;

		qcom,pm-qos-legacy-latency-us = <43 43>;



		clocks = <&gcc GCC_SDCC1_AHB_CLK>,

			<&gcc GCC_SDCC1_APPS_CLK>,

			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
@@ -881,6 +888,8 @@ 


		qcom,ice-clk-rates = <300000000 100000000>;



		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */

		qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>;

		qcom,nonremovable;

		status = "disabled";

	};
@@ -904,9 +913,19 @@ 


		qcom,devfreq,freq-table = <50000000 202000000>;



		/* PM QoS */

		qcom,pm-qos-irq-type = "affine_irq";

		qcom,pm-qos-irq-latency = <43 43>;

		qcom,pm-qos-cpu-groups = <0x0f>;

		qcom,pm-qos-legacy-latency-us = <43 43>;



		clocks = <&gcc GCC_SDCC2_AHB_CLK>,

			<&gcc GCC_SDCC2_APPS_CLK>;

		clock-names = "iface_clk", "core_clk";



		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */

		qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>;



		status = "disabled";

	};