staging/trivial: fix typos concerning "address"

#define bar0_window	dev_dep[0x80 - 0x40]

#define bar1_window	dev_dep[0x84 - 0x40]

#define sprom_control	dev_dep[0x88 - 0x40]

#define	PCI_BAR0_WIN		0x80	/* backplane addres space accessed by BAR0 */

#define	PCI_BAR1_WIN		0x84	/* backplane addres space accessed by BAR1 */

#define	PCI_BAR0_WIN		0x80	/* backplane address space accessed by BAR0 */

#define	PCI_BAR1_WIN		0x84	/* backplane address space accessed by BAR1 */

#define	PCI_SPROM_CONTROL	0x88	/* sprom property control */

#define	PCI_BAR1_CONTROL	0x8c	/* BAR1 region burst control */

#define	PCI_INT_STATUS		0x90	/* PCI and other cores interrupts */

#define PCI_BACKPLANE_ADDR	0xa0	/* address an arbitrary location on the system backplane */

#define PCI_BACKPLANE_DATA	0xa4	/* data at the location specified by above address */

#define	PCI_CLK_CTL_ST		0xa8	/* pci config space clock control/status (>=rev14) */

#define	PCI_BAR0_WIN2		0xac	/* backplane addres space accessed by second 4KB of BAR0 */

#define	PCI_BAR0_WIN2		0xac	/* backplane address space accessed by second 4KB of BAR0 */

#define	PCI_GPIO_IN		0xb0	/* pci config space gpio input (>=rev3) */

#define	PCI_GPIO_OUT		0xb4	/* pci config space gpio output (>=rev3) */

#define	PCI_GPIO_OUTEN		0xb8	/* pci config space gpio output enable (>=rev3) */

} dma64dd_t;

/*

 * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.

 * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical address.

 */

#define D64RINGALIGN_BITS	13

#define	D64MAXRINGSZ		(1 << D64RINGALIGN_BITS)

	}

	info->stats.tx_packets++;

	// Add 14 bytes for MAC adddress plus ethernet type

	// Add 14 bytes for MAC address plus ethernet type

	info->stats.tx_bytes += (len + 14);

	return SUCCESS;

}