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Commit ae78fd95 authored by Shivendra Kakrania's avatar Shivendra Kakrania
Browse files

techpack: video: Updating video kernel snapshot 



Video kernel snapshot before disabling msm/vidc compilation
from base kernel.

Change-Id: Id1178c3aca00706ad4822537f7f9a28141478771
Signed-off-by: default avatarShivendra Kakrania <shiven@codeaurora.org>
parent 4ae4cb17

msm/Makefile

+4 −1
Original line number Diff line number Diff line
@@ -14,7 +14,10 @@ msm-vidc-objs := vidc/msm_v4l2_vidc.o \ 
                vidc/msm_smem.o \

                vidc/msm_vidc_debug.o \

                vidc/msm_vidc_res_parse.o \

                vidc/venus_hfi.o \

                vidc/hfi_common.o \

                vidc/hfi_ar50.o \

                vidc/hfi_iris1.o \

                vidc/hfi_iris2.o \

                vidc/hfi_response_handler.o \

                vidc/hfi_packetization.o \

                vidc/vidc_hfi.o \

msm/vidc/hfi_ar50.c

0 → 100644
+13 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#include "hfi_common.h"

#include "hfi_io_common.h"



void __interrupt_init_ar50(struct venus_hfi_device *device)

{

	__write_register(device, WRAPPER_INTR_MASK,

			WRAPPER_INTR_MASK_A2HVCODEC_BMSK);

}

msm/vidc/venus_hfi.c→msm/vidc/hfi_common.c

+160 −336

File changed and moved.

Preview size limit exceeded, changes collapsed.

msm/vidc/venus_hfi.h→msm/vidc/hfi_common.h

+35 −4
Original line number Diff line number Diff line
@@ -3,8 +3,8 @@ 
 * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.

 */



#ifndef __H_VENUS_HFI_H__

#define __H_VENUS_HFI_H__

#ifndef __HFI_COMMON_H__

#define __HFI_COMMON_H__



#include <linux/clk.h>

#include <linux/mutex.h>
@@ -234,12 +234,17 @@ enum reset_state { 
struct venus_hfi_device;



struct venus_hfi_vpu_ops {

	void (*interrupt_init)(struct venus_hfi_device *ptr);

	void (*setup_dsp_uc_memmap)(struct venus_hfi_device *device);

	void (*interrupt_init)(struct venus_hfi_device *device);

	void (*setup_ucregion_memmap)(struct venus_hfi_device *device);

	void (*clock_config_on_enable)(struct venus_hfi_device *device);

	int (*reset_ahb2axi_bridge)(struct venus_hfi_device *device);

	void (*power_off)(struct venus_hfi_device *device);

	int (*prepare_pc)(struct venus_hfi_device *device);

	void (*raise_interrupt)(struct venus_hfi_device *device);

	bool (*watchdog)(u32 intr_status);

	void (*noc_error_info)(struct venus_hfi_device *device);

	void (*core_clear_interrupt)(struct venus_hfi_device *device);

	int (*boot_firmware)(struct venus_hfi_device *device);

};



struct venus_hfi_device {
@@ -286,4 +291,30 @@ int venus_hfi_initialize(struct hfi_device *hdev, u32 device_id, 
		struct msm_vidc_platform_resources *res,

		hfi_cmd_response_callback callback);



void __write_register(struct venus_hfi_device *device, u32 reg, u32 value);

int __read_register(struct venus_hfi_device *device, u32 reg);

void __disable_unprepare_clks(struct venus_hfi_device *device);

int __disable_regulators(struct venus_hfi_device *device);

int __unvote_buses(struct venus_hfi_device *device);

int __reset_ahb2axi_bridge_common(struct venus_hfi_device *device);

int __prepare_pc(struct venus_hfi_device *device);



/* AR50 specific */

void __interrupt_init_ar50(struct venus_hfi_device *device);

/* IRIS1 specific */

void __interrupt_init_iris1(struct venus_hfi_device *device);

void __setup_dsp_uc_memmap_iris1(struct venus_hfi_device *device);

void __clock_config_on_enable_iris1(struct venus_hfi_device *device);

void __setup_ucregion_memory_map_iris1(struct venus_hfi_device *device);

/* IRIS2 specific */

void __interrupt_init_iris2(struct venus_hfi_device *device);

void __setup_ucregion_memory_map_iris2(struct venus_hfi_device *device);

void __power_off_iris2(struct venus_hfi_device *device);

int __prepare_pc_iris2(struct venus_hfi_device *device);

void __raise_interrupt_iris2(struct venus_hfi_device *device);

bool __watchdog_iris2(u32 intr_status);

void __noc_error_info_iris2(struct venus_hfi_device *device);

void __core_clear_interrupt_iris2(struct venus_hfi_device *device);

int __boot_firmware_iris2(struct venus_hfi_device *device);



#endif

msm/vidc/hfi_io_common.h

0 → 100644
+139 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef __HFI_IO_COMMON_H__

#define __HFI_IO_COMMON_H__



#include <linux/io.h>



#define VBIF_BASE_OFFS			0x00080000



#define CPU_BASE_OFFS			0x000C0000

#define CPU_CS_BASE_OFFS		(CPU_BASE_OFFS + 0x00012000)

#define CPU_IC_BASE_OFFS		(CPU_BASE_OFFS + 0x0001F000)



#define CPU_CS_A2HSOFTINT		(CPU_CS_BASE_OFFS + 0x18)

#define CPU_CS_A2HSOFTINTCLR	(CPU_CS_BASE_OFFS + 0x1C)

#define CPU_CS_VMIMSG		(CPU_CS_BASE_OFFS + 0x34)

#define CPU_CS_VMIMSGAG0		(CPU_CS_BASE_OFFS + 0x38)

#define CPU_CS_VMIMSGAG1		(CPU_CS_BASE_OFFS + 0x3C)

#define CPU_CS_SCIACMD			(CPU_CS_BASE_OFFS + 0x48)



/* HFI_CTRL_STATUS */

#define CPU_CS_SCIACMDARG0		(CPU_CS_BASE_OFFS + 0x4C)

#define CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK	0xfe

#define CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY           0x100

#define CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK     0x40000000



/* HFI_QTBL_INFO */

#define CPU_CS_SCIACMDARG1		(CPU_CS_BASE_OFFS + 0x50)



/* HFI_QTBL_ADDR */

#define CPU_CS_SCIACMDARG2		(CPU_CS_BASE_OFFS + 0x54)



/* HFI_VERSION_INFO */

#define CPU_CS_SCIACMDARG3		(CPU_CS_BASE_OFFS + 0x58)



/* SFR_ADDR */

#define CPU_CS_SCIBCMD		(CPU_CS_BASE_OFFS + 0x5C)



/* MMAP_ADDR */

#define CPU_CS_SCIBCMDARG0		(CPU_CS_BASE_OFFS + 0x60)



/* UC_REGION_ADDR */

#define CPU_CS_SCIBARG1		(CPU_CS_BASE_OFFS + 0x64)



/* UC_REGION_ADDR */

#define CPU_CS_SCIBARG2		(CPU_CS_BASE_OFFS + 0x68)



#define CPU_IC_SOFTINT			(CPU_IC_BASE_OFFS + 0x18)

#define CPU_IC_SOFTINT_H2A_SHFT	0xF



/*

 * --------------------------------------------------------------------------

 * MODULE: wrapper

 * --------------------------------------------------------------------------

 */

#define WRAPPER_BASE_OFFS		0x000E0000

#define WRAPPER_INTR_STATUS	(WRAPPER_BASE_OFFS + 0x0C)

#define WRAPPER_INTR_STATUS_A2HWD_BMSK	0x10

#define WRAPPER_INTR_STATUS_A2H_BMSK	0x4



#define WRAPPER_INTR_MASK		(WRAPPER_BASE_OFFS + 0x10)

#define WRAPPER_INTR_MASK_A2HWD_BMSK	0x10

#define WRAPPER_INTR_MASK_A2HVCODEC_BMSK	0x8

#define WRAPPER_INTR_MASK_A2HCPU_BMSK	0x4

#define WRAPPER_INTR_CLEAR		(WRAPPER_BASE_OFFS + 0x14)



#define WRAPPER_CPU_CLOCK_CONFIG	(WRAPPER_BASE_OFFS + 0x2000)

#define WRAPPER_CPU_CGC_DIS	(WRAPPER_BASE_OFFS + 0x2010)

#define WRAPPER_CPU_STATUS (WRAPPER_BASE_OFFS + 0x2014)



#define CTRL_INIT		CPU_CS_SCIACMD



#define CTRL_STATUS	CPU_CS_SCIACMDARG0

#define CTRL_ERROR_STATUS__M \

		CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK

#define CTRL_INIT_IDLE_MSG_BMSK \

		CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK

#define CTRL_STATUS_PC_READY \

		CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY





#define QTBL_INFO		CPU_CS_SCIACMDARG1



#define QTBL_ADDR		CPU_CS_SCIACMDARG2



#define VERSION_INFO	CPU_CS_SCIACMDARG3



#define SFR_ADDR		CPU_CS_SCIBCMD

#define MMAP_ADDR		CPU_CS_SCIBCMDARG0

#define UC_REGION_ADDR	CPU_CS_SCIBARG1

#define UC_REGION_SIZE	CPU_CS_SCIBARG2



/* HFI_DSP_QTBL_ADDR

 * 31:3 - HFI_DSP_QTBL_ADDR

 *        4-byte aligned Address

 */

#define HFI_DSP_QTBL_ADDR	CPU_CS_VMIMSG



/* HFI_DSP_UC_REGION_ADDR

 * 31:20 - HFI_DSP_UC_REGION_ADDR

 *         1MB aligned address.

 *         Uncached Region start Address. This region covers

 *         HFI DSP QTable,

 *         HFI DSP Queue Headers,

 *         HFI DSP Queues,

 */

#define HFI_DSP_UC_REGION_ADDR	CPU_CS_VMIMSGAG0



/* HFI_DSP_UC_REGION_SIZE

 * 31:20 - HFI_DSP_UC_REGION_SIZE

 *         Multiples of 1MB.

 *         Size of the DSP_UC_REGION Uncached Region

 */

#define HFI_DSP_UC_REGION_SIZE	CPU_CS_VMIMSGAG1



/*

 * --------------------------------------------------------------------------

 * MODULE: vcodec noc error log registers

 * --------------------------------------------------------------------------

 */

#define VCODEC_CORE0_VIDEO_NOC_BASE_OFFS		0x00004000

#define VCODEC_CORE1_VIDEO_NOC_BASE_OFFS		0x0000C000

#define VCODEC_COREX_VIDEO_NOC_ERR_SWID_LOW_OFFS	0x0500

#define VCODEC_COREX_VIDEO_NOC_ERR_SWID_HIGH_OFFS	0x0504

#define VCODEC_COREX_VIDEO_NOC_ERR_MAINCTL_LOW_OFFS	0x0508

#define VCODEC_COREX_VIDEO_NOC_ERR_ERRVLD_LOW_OFFS	0x0510

#define VCODEC_COREX_VIDEO_NOC_ERR_ERRCLR_LOW_OFFS	0x0518

#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG0_LOW_OFFS	0x0520

#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG0_HIGH_OFFS	0x0524

#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG1_LOW_OFFS	0x0528

#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG1_HIGH_OFFS	0x052C

#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG2_LOW_OFFS	0x0530

#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG2_HIGH_OFFS	0x0534

#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG3_LOW_OFFS	0x0538

#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG3_HIGH_OFFS	0x053C

#endif